公开(公告)号：US20150171535A1

公开(公告)日：2015-06-18

申请号：US13994023

申请日：2011-12-28

申请人： Xiang Li ,  Chong J. Zhao ,  Jefferey L. Krieger ,  Dan Willis ,  John M. Lynch ,  Yun Ling

发明人： Xiang Li ,  Chong J. Zhao ,  Jefferey L. Krieger ,  Dan Willis ,  John M. Lynch ,  Yun Ling

IPC分类号： H01R12/73 ,  H05K1/18

CPC分类号： H01R12/732 ,  H01R12/721 ,  H01R12/83 ,  H05K1/181 ,  H05K2201/10159

摘要： According to some embodiments, a SODIMM memory connector comprises a first socket to electrically couple a first SODIMM, and a second socket to electrically couple a second SODIMM, where the first socket is disposed vertically adjacent to the second socket.

摘要翻译： 根据一些实施例，SODIMM存储器连接器包括用于电耦合第一SODIMM的第一插座和用于电耦合第二SODIMM的第二插座，其中第一插座垂直地邻近第二插座设置。

公开(公告)号：US20160183374A1

公开(公告)日：2016-06-23

申请号：US14575775

申请日：2014-12-18

申请人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

发明人： Mani Prakash ,  Thomas T. Holden ,  Jeffory L. Smalley ,  Ram S. Viswanath ,  Bassam N. Coury ,  Dimitrios Ziakas ,  Chong J. Zhao ,  Jonathan W. Thibado ,  Gregorio R. Murtagian ,  Kuang C. Liu ,  Rajasekaran Swaminathan ,  Zhichao Zhang ,  John M. Lynch ,  David J. Llapitan ,  Sanka Ganesan ,  Xiang Li ,  George Vergis

IPC分类号： H05K1/18 ,  H01R12/72 ,  H05K1/11 ,  H05K1/02 ,  H05K3/30 ,  H05K3/34

CPC分类号： H05K1/181 ,  H01L23/00 ,  H01L23/498 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01R12/712 ,  H01R12/79 ,  H05K2201/10159 ,  H05K2201/10325 ,  Y02P70/611

摘要： Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.

摘要翻译： 公开了可配置的中央处理单元（CPU）封装基板。 描述了包括处理设备接口的封装衬底。 封装衬底还包括设置在封装衬底上的存储器件电接口。 封装衬底还包括靠近存储器件电接口设置的可移除存储器机械接口。 可移除存储器机械接口是允许在将存储器件附接到封装衬底之后容易地从封装衬底移除存储器件。

公开(公告)号：US20150340817A1

公开(公告)日：2015-11-26

申请号：US14286494

申请日：2014-05-23

申请人： Xiang Li ,  Hao-Han Hsu ,  Yun Ling ,  Gong Ouyang ,  Kai Xiao ,  Jiangqi He ,  Lu-Vong T. Phan ,  Wei Xu

发明人： Xiang Li ,  Hao-Han Hsu ,  Yun Ling ,  Gong Ouyang ,  Kai Xiao ,  Jiangqi He ,  Lu-Vong T. Phan ,  Wei Xu

IPC分类号： H01R13/6598 ,  H01R43/18 ,  H05K3/36 ,  H01R12/72 ,  H05K3/28

CPC分类号： H01R13/6598 ,  H01R12/712 ,  H01R12/721 ,  H01R12/724 ,  H01R13/658 ,  H01R43/18 ,  H05K3/284 ,  H05K3/36 ,  Y10T29/49128

摘要： In an embodiment, a connector such as an edge connector includes a connector housing, a first set of pins configured within the housing and having first ends to couple to corresponding signal lines of a first circuit board and second ends to couple to corresponding signal lines of a mating connector of a second circuit board, and a conductive material adapted to the housing to reduce interference caused by one or more sources of interference. Other embodiments are described and claimed.

摘要翻译： 在一个实施例中，诸如边缘连接器的连接器包括连接器壳体，构造在壳体内的第一组引脚，并且具有耦合到第一电路板的相应信号线的第一端和第二端耦合到相应的信号线 第二电路板的配合连接器以及适于壳体的导电材料，以减少由一个或多个干扰源造成的干扰。 描述和要求保护其他实施例。

公开(公告)号：US20140377968A1

公开(公告)日：2014-12-25

申请号：US13996004

申请日：2011-12-23

申请人： Michael Leddige ,  Yun Ling ,  Kuan-Yu Chen ,  Kai Wang ,  Xiang Li ,  Howard Heck

发明人： Michael Leddige ,  Yun Ling ,  Kuan-Yu Chen ,  Kai Wang ,  Xiang Li ,  Howard Heck

IPC分类号： H01R4/48 ,  H01R43/18 ,  H01R12/71

CPC分类号： H01R4/48 ,  H01R12/71 ,  H01R12/716 ,  H01R12/721 ,  H01R13/24 ,  H01R13/6658 ,  H01R43/18 ,  Y10T29/49208

摘要： Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.

摘要翻译： 支持输入输出（IO）通信的方法和系统可以包括具有壳体的IO连接器，所述壳体具有限定桨卡区域的表面，以及一组垂直延伸穿过壳体进入桨卡区域的可压缩触点。 此外，IO互连可以包括电缆部分和耦合到电缆部分的至少一个端部部分。 端部可以包括具有电路板的桨卡，该电路板具有布置在电路板的底表面上的一组触点。 端部部分还可以包括不对称的金属壳体，该壳体具有包围桨片的至少一部分并且暴露该组触点的构造。

公开(公告)号：US09391378B2

公开(公告)日：2016-07-12

申请号：US13996004

申请日：2011-12-23

申请人： Michael Leddige ,  Yun Ling ,  Kuan-Yu Chen ,  Kai Wang ,  Xiang Li ,  Howard Heck

发明人： Michael Leddige ,  Yun Ling ,  Kuan-Yu Chen ,  Kai Wang ,  Xiang Li ,  Howard Heck

IPC分类号： H01R4/48 ,  H01R12/72 ,  H01R13/24 ,  H01R12/71 ,  H01R43/18 ,  H01R13/66

CPC分类号： H01R4/48 ,  H01R12/71 ,  H01R12/716 ,  H01R12/721 ,  H01R13/24 ,  H01R13/6658 ,  H01R43/18 ,  Y10T29/49208

摘要： Methods and systems to support input output (IO) communications may include an IO connector having a housing with surfaces defining a paddle card region, and a set of compressible contacts extending vertically through the housing into the paddle card region. In addition, an IO interconnect can include a cable portion and at least one end portion coupled to the cable portion. The end portion may include a paddle card having a circuit board with a set of contacts disposed on a bottom surface of the circuit board. The end portion can also include an asymmetric metal shell having a configuration that encloses at least a portion of the paddle card and exposes the set of contacts.

摘要翻译： 支持输入输出（IO）通信的方法和系统可以包括具有壳体的IO连接器，所述壳体具有限定桨卡区域的表面，以及一组垂直延伸穿过壳体进入桨卡区域的可压缩触点。 此外，IO互连可以包括电缆部分和耦合到电缆部分的至少一个端部部分。 端部可以包括具有电路板的桨卡，该电路板具有布置在电路板的底表面上的一组触点。 端部部分还可以包括不对称的金属壳体，该壳体具有包围桨片的至少一部分并且暴露该组触点的构造。

公开(公告)号：US20150280343A1

公开(公告)日：2015-10-01

申请号：US14227009

申请日：2014-03-27

申请人： Hao-Han Hsu ,  Yun Ling ,  Xiang Li

发明人： Hao-Han Hsu ,  Yun Ling ,  Xiang Li

IPC分类号： H01R13/24 ,  H01R43/16 ,  H01R13/6581

CPC分类号： H01R13/2421 ,  H01R12/724 ,  H01R13/4538 ,  H01R13/6583 ,  H01R2201/06 ,  Y10T29/49222

摘要： In accordance with some embodiments, a high speed connection may be implemented using pogo-pins. The use of pogo-pins may be advantageous because accurate alignment is not required, connection force is generally lower than with other connections and appearance is often highly advantageous. Through the use of a moveable metal shield, an advantageous high speed connection for high speed signaling may be implemented between the two devices.

摘要翻译： 根据一些实施例，可以使用弹簧针来实现高速连接。 使用弹簧销可能是有利的，因为不需要精确对准，连接力通常低于与其它连接件的连接力，并且外观通常是非常有利的。 通过使用可移动金属屏蔽，可以在两个装置之间实现用于高速信号的有利的高速连接。

公开(公告)号：US20230046581A1

公开(公告)日：2023-02-16

申请号：US17728099

申请日：2022-04-25

申请人： Xiang Li ,  Shaohua Li ,  Landon Hanks ,  Kai Xiao ,  Mo Liu ,  Jingbo Li

发明人： Xiang Li ,  Shaohua Li ,  Landon Hanks ,  Kai Xiao ,  Mo Liu ,  Jingbo Li

IPC分类号： H05K7/10 ,  G06F13/40

摘要： An apparatus and method for reducing differential cross-talk in a pin arrangement of a socket are described. Socket pins within a differential pair use a modified shape to tighten the intra-pair pin coupling to reduce the crosstalk without changing the pin map. The middle vertical segment of one pin of a diagonally adjacent differential pin pair is modified to be closer to the other pin than other corresponding locations of the pins. The spring beam that extends from the middle vertical segment of the one pin is modified to accommodate the package landing pad that the spring beam contacts to maintain a uniform pitch.

公开(公告)号：US09787028B2

公开(公告)日：2017-10-10

申请号：US13997893

申请日：2012-03-31

申请人： Raul Enriquez-Shibayama ,  Kai Xiao ,  Xiang Li

发明人： Raul Enriquez-Shibayama ,  Kai Xiao ,  Xiang Li

IPC分类号： H01R13/6461 ,  H01R12/73 ,  H01R13/6471

CPC分类号： H01R13/6461 ,  H01R12/737 ,  H01R13/6471 ,  H01R2201/06

摘要： Apparatus and methods of arranging ground pins and signal pins in a card connector includes arranging a signal pins and ground pins in a card connector into at least six (6) columns divided between a primary side and a secondary side of the connector.

公开(公告)号：US09281540B2

公开(公告)日：2016-03-08

申请号：US13514973

申请日：2010-12-06

申请人： Xiang Li ,  Jie Tang ,  Qingjin Sun ,  Sheng Xu ,  Jianhai Luo

发明人： Xiang Li ,  Jie Tang ,  Qingjin Sun ,  Sheng Xu ,  Jianhai Luo

IPC分类号： H01M2/14 ,  H01M2/16 ,  H01M10/02 ,  H01M10/04 ,  H01M10/0525 ,  H01M4/62 ,  H01M4/66

CPC分类号： H01M10/0525 ,  H01M2/1653 ,  H01M2/166 ,  H01M2/1686 ,  H01M4/13 ,  H01M4/133 ,  H01M4/136 ,  H01M4/485 ,  H01M4/587 ,  H01M4/62 ,  H01M4/625 ,  H01M4/661 ,  H01M10/056 ,  H01M2300/0068 ,  H01M2300/0091 ,  Y02E60/122

摘要： A lithium-ion battery comprises a positive electrode, a negative electrode, an electrolyte system and an ion-selective conducting layer disposed between the positive electrode and the negative electrode. The ion-selective conducting layer consists of high polymers and an inorganic lithium salt having lithium-ion conductivity, or consists of the inorganic lithium salt. The inorganic lithium salt includes LimMnOx, wherein the values of the m and n ensure the LimMnOx an electrically neutral compound, M is selected from at least one of B, P, Si, Se, Zr, W, Ti, Te, Ta, Al and As. The lithium-ion battery has a conduction layer having preference-selective conductivity for the lithium ions and disposed between the positive electrode and the negative electrode. The selective-conduction layer has improved mobility for lithium ions. Metal ions generated from the oxidized metal current collector at the negative electrode due to the over-charging of the battery can be blocked.

摘要翻译： 锂离子电池包括正极，负极，电解质体系和配置在正极和负极之间的离子选择性导电层。 离子选择导电层由高分子聚合物和具有锂离子传导性的无机锂盐组成，或由无机锂盐组成。 无机锂盐包括LimMnOx，其中m和n的值确保LimMnOx为电中性的化合物，M选自B，P，Si，Se，Zr，W，Ti，Te，Ta，Al中的至少一种 并作为。 锂离子电池具有对于锂离子具有优选选择性导电性的导电层并且设置在正极和负极之间。 选择导电层具有改善的锂离子的迁移率。 可以阻止由于电池的过充电而从负极处的氧化金属集电体产生的金属离子。

公开(公告)号：US09153697B2

公开(公告)日：2015-10-06

申请号：US13116506

申请日：2011-05-26

申请人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  King-Jien Chui ,  Yisuo Li ,  Yu Jiang ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

发明人： Fujio Masuoka ,  Hiroki Nakamura ,  Shintaro Arai ,  Tomohiko Kudo ,  King-Jien Chui ,  Yisuo Li ,  Yu Jiang ,  Xiang Li ,  Zhixian Chen ,  Nansheng Shen ,  Vladimir Bliznetsov ,  Kavitha Devi Buddharaju ,  Navab Singh

IPC分类号： H01L21/70 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66 ,  H01L21/265

CPC分类号： H01L29/42392 ,  H01L21/26586 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823871 ,  H01L21/823885 ,  H01L27/088 ,  H01L27/092 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/4958 ,  H01L29/66666 ,  H01L29/66772 ,  H01L29/78618 ,  H01L29/78642 ,  H01L29/78696

摘要： The semiconductor device according to the present invention is an nMOS SGT and is composed of a first n+ type silicon layer, a first gate electrode containing metal and a second n+ type silicon layer arranged on the surface of a first columnar silicon layer positioned vertically on a first planar silicon layer. Furthermore, a first insulating film is positioned between the first gate electrode and the first planar silicon layer, and a second insulating film is positioned on the top surface of the first gate electrode. In addition, the first gate electrode containing metal is surrounded by the first n+ type silicon layer, the second n+ type silicon layer, the first insulating film and the second insulating film.

摘要翻译： 根据本发明的半导体器件是nMOS SGT，并且由第一n +型硅层，含有金属的第一栅电极和第二n +型硅层构成，所述第二n +型硅层布置在垂直定位在第一n +型硅层上的第一柱状硅层的表面上 第一平面硅层。 此外，第一绝缘膜位于第一栅电极和第一平面硅层之间，第二绝缘膜位于第一栅电极的顶表面上。 此外，含有第一栅电极的金属被第一n +型硅层，第二n +型硅层，第一绝缘膜和第二绝缘膜包围。