公开(公告)号：US09988668B2

公开(公告)日：2018-06-05

申请号：US14128486

申请日：2012-06-25

申请人： Zhimin Ding ,  Fang Wu ,  Li Liu

发明人： Zhimin Ding ,  Fang Wu ,  Li Liu

IPC分类号： C12M1/34 ,  C12Q1/68 ,  B01L7/00

CPC分类号： C12Q1/6806 ,  B01L7/52 ,  B01L2200/028 ,  B01L2200/147 ,  B01L2200/148 ,  B01L2200/16 ,  B01L2300/043 ,  B01L2300/0654 ,  B01L2300/1822 ,  B01L2300/1827

摘要： Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

公开(公告)号：US20140329244A1

公开(公告)日：2014-11-06

申请号：US14128486

申请日：2012-06-25

申请人： Zhimin Ding ,  Fang Wu ,  Li Liu

发明人： Zhimin Ding ,  Fang Wu ,  Li Liu

IPC分类号： C12Q1/68

CPC分类号： C12Q1/6806 ,  B01L7/52 ,  B01L2200/028 ,  B01L2200/147 ,  B01L2200/148 ,  B01L2200/16 ,  B01L2300/043 ,  B01L2300/0654 ,  B01L2300/1822 ,  B01L2300/1827

摘要： Described herein is a chip-based apparatus for amplifying nucleic acids, a cartridge housing the apparatus, and methods of using the apparatus for amplification of nucleic acids. More specifically, this invention provides integrated semiconductor chip, manufactured with standard semiconductor manufacturing process, with on-chip circuitry to perform thermal management and optical sensing necessary for amplification of nucleic acids. The apparatus and methods embodied in this invention makes it possible to build a disease diagnosis and prognosis tool that is easy to use, portable and disposable.

摘要翻译： 本文描述了用于扩增核酸的基于芯片的装置，容纳该装置的盒和使用用于扩增核酸的装置的方法。 更具体地，本发明提供了具有标准半导体制造工艺制造的集成半导体芯片，具有片上电路以执行核酸扩增所需的热管理和光学感测。 本发明实施的装置和方法使得构建易于使用，便携和一次性的疾病诊断和预后工具成为可能。

公开(公告)号：US20090075698A1

公开(公告)日：2009-03-19

申请号：US11855846

申请日：2007-09-14

申请人： Zhimin Ding ,  Richard M. Morley ,  Stephen Johnston ,  Bing Yeh ,  John E. Berg

发明人： Zhimin Ding ,  Richard M. Morley ,  Stephen Johnston ,  Bing Yeh ,  John E. Berg

IPC分类号： H04B1/38

CPC分类号： H04W8/245 ,  H04W48/08 ,  H04W48/18 ,  H04W88/06

摘要： A removable card for use with a mobile wireless communication device has a processor and a non-volatile memory, connected to the processor. The memory has programming code stored configured to be executed by the processor and is operable in one of two modes. In a first mode the card is connected to the device with the card storing information received wirelessly by the device from the Internet. In a second mode the card is connected to a network portal device, which is connected to the Internet, with the card storing information received through the network portal device from the Internet. In another embodiment, the removable card has electrical connections for connecting to a mobile wireless communicating device for use by a user to connect to the Internet. The memory has two portions: a first portion and a second portion with the partitioning being alterable. The processor restricts access to the first portion by the user, while grants access to the second portion to the user. Finally, the present invention relates to a mobile wireless communication device.

摘要翻译： 用于移动无线通信设备的可拆卸卡具有连接到处理器的处理器和非易失性存储器。 存储器具有被配置为由处理器执行并且可以以两种模式之一操作的存储的编程代码。 在第一模式中，卡被连接到设备，其中卡存储由设备从因特网无线地接收到的信息。 在第二模式中，该卡连接到连接到互联网的网络入口设备，其中卡从存储通过网络入口设备从因特网接收的信息。 在另一个实施例中，可拆卸卡具有用于连接到移动无线通信设备的电连接，供用户使用以连接到因特网。 存储器具有两部分：第一部分和第二部分，其中分割是可改变的。 处理器限制用户对第一部分的访问，同时向用户授予对第二部分的访问。 最后，本发明涉及移动无线通信设备。

公开(公告)号：US20060206691A1

公开(公告)日：2006-09-14

申请号：US10566514

申请日：2004-07-27

申请人： Gregory Goodhue ,  Ata Khan ,  Zhimin Ding

发明人： Gregory Goodhue ,  Ata Khan ,  Zhimin Ding

IPC分类号： G06F9/40

CPC分类号： G06F9/321 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/3016 ,  G06F9/35

摘要： All Pointer-based accesses require first that the value contained in a pointer register (200a, 200b, 200c, 200d) to be read and then that value be used as an address to the appropriate region in random access memory (RAM) (104). As implemented today, this requires two memory read access cycles, each of which takes at least one clock cycle and therefore this implementation does not allow single cycle operation. In accordance with an embodiment of the invention, when an access is performed to pointer memory (103a, 103b, 103c, 103d) to read the contents of a pointer, it is the shadow memory that is actually read and that returns the pointer value. Since the shadow memory is made up of pointer registers (200a, 200b, 200c, 200d), a read access involves mutliplexing out of appropriate data for the pointer address from these pointer registers (200a, 200b, 200c, 200d) to form a target pointer address. This target pointer address is then used as an address to access RAM (104) without the overhead of a clock, since the register access is purely combinatorial and does not require clock-phase related timing as does access to the RAM (104).

摘要翻译： 所有基于指针的访问首先需要读取指针寄存器（200a，200b，200c，200d）中包含的值，然后将该值用作随机存取存储器（RAM）中适当区域的地址 （104）。 如今所实现的，这需要两个存储器读取访问周期，每个存储器访问周期至少需要一个时钟周期，因此该实现不允许单周期操作。 根据本发明的实施例，当对指针存储器（103a，103b，103c，103d）执行访问以读取指针的内容时，实际上是读取的影子存储器，并且返回 指针值。 由于阴影存储器由指针寄存器（200a，200b，200c，200d）组成，所以读取访问涉及从这些指针寄存器（200a，200b，200c）中针对指针地址的适当数据进行多路复用 ，200 d）以形成目标指针地址。 然后，该目标指针地址用作访问RAM（104）的地址，而不需要时钟的开销，因为寄存器访问是纯组合的，并且不需要与访问RAM（104）一样的时钟相位相关定时。

公开(公告)号：US20060206646A1

公开(公告)日：2006-09-14

申请号：US10566515

申请日：2004-07-29

申请人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig Mackenna

发明人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig Mackenna

IPC分类号： G06F13/24 ,  G06F13/36

CPC分类号： G06F9/4812 ,  G06F9/462 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

摘要： Typically, for processing systems it must be guaranteed that all interrupted program stream parameters are restored before the execution of the first program stream resumes. If during this transfer an interrupt occurs, then all data may not be stored or restored. If the error free storage of the program register contents and other critical first program stream data does not occur, the processor (180) has no way of knowing whether the first program stream data restored to the registers has become corrupt or not. Thus, a novel register architecture (120, 121, 122, 123, 124, 125) is provided that facilitate processing of interrupting program streams without storing and restoring interrupted program stream critical data.

摘要翻译： 通常，对于处理系统，必须保证在第一个程序流的执行恢复之前所有中断的程序流参数都被恢复。 如果在此传输期间发生中断，则所有数据可能不被存储或恢复。 如果不发生程序寄存器内容和其他关键的第一程序流数据的无错误存储，则处理器（180）无法知道还原到寄存器的第一程序流数据是否已经被破坏。 因此，提供了一种新颖的寄存器架构（120,121,122,123,124,125），其便于中断程序流的处理，而不存储和恢复中断的程序流关键数据。

公开(公告)号：US06526463B1

公开(公告)日：2003-02-25

申请号：US09548988

申请日：2000-04-14

申请人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

发明人： Zhimin Ding ,  Gregory K. Goodhue ,  Ata R. Khan

IPC分类号： G06F942

CPC分类号： G06F9/342 ,  G06F9/30043 ,  G06F9/30163 ,  G06F9/30189 ,  G06F9/4486 ,  G06F9/4812

摘要： A processing system with extended addressing capabilities includes a control bit that controls the number of address bytes that are stored onto a program stack. If the control bit is set to a first state, the address is pushed onto the program stack in the same manner as that used for shorter-address legacy devices. If the control bit is set to a second state, the address is pushed onto the program stack using the number of bytes required to contain a longer extended address. This same control bit controls the number of bytes that are popped off the stack upon return from an interrupt subroutine. The state of the control bit is controlled by one or more program instructions, thereby allowing it to assume each state dynamically. This dynamic control of the number of bytes pushed and popped to and from the stack allows for an optimization of stack utilization, and thereby further compatibility with legacy devices and applications.

摘要翻译： 具有扩展寻址能力的处理系统包括控制位，该控制位控制存储在程序堆栈上的地址字节数。 如果控制位设置为第一状态，则以与用于较短地址的传统设备相同的方式将地址推送到程序堆栈。 如果控制位设置为第二个状态，则使用包含较长扩展地址所需的字节数将该地址推送到程序堆栈。 相同的控制位控制从中断子程序返回时从堆栈弹出的字节数。 控制位的状态由一个或多个程序指令控制，从而允许其动态地呈现每个状态。 对堆栈和从堆栈进行弹出的字节数的这种动态控制允许优化堆栈利用率，从而进一步与传统设备和应用程序的兼容性。

公开(公告)号：US07979717B2

公开(公告)日：2011-07-12

申请号：US12100400

申请日：2008-04-09

申请人： Zhimin Ding

发明人： Zhimin Ding

IPC分类号： G06F21/00 ,  H04M1/00

CPC分类号： H04L9/0825 ,  H04L9/0894 ,  H04L2209/80

摘要： A secure removable card has electrical connections for communication therewith. The card comprises a first integrated circuit die, with the first die including a processor. The card has a second integrated circuit die, with the second die including a non-volatile memory for storing a secret key, and a controller for controlling the operation of the non-volatile memory. A bus connects the first die with the second die. The processor can generate a key pair, having a public key portion and a private key portion upon power up, and transfers the public key portion across the bus to the second die. The controller can receive the public key and encrypt the secret key with the public key to generate a first encrypted key, and can transfer the first encrypted key across the bus to the first die. The processor can receive the first encrypted key and can decrypt the first encrypted key to recover the secret key, and can encrypt data with the secret key for communicating along the electrical connections external to the card.

摘要翻译： 安全的可拆卸卡具有用于与之通信的电连接。 该卡包括第一集成电路管芯，其中第一管芯包括处理器。 卡具有第二集成电路管芯，第二管芯包括用于存储秘密密钥的非易失性存储器，以及用于控制非易失性存储器的操作的控制器。 总线连接第一个模具和第二个模具。 处理器可以在上电时生成具有公钥部分和私钥部分的密钥对，并且将公共密钥部分跨越总线传送到第二管芯。 控制器可以接收公开密钥并用公开密钥加密秘密密钥，以产生第一个加密密钥，并且可以将总线上的第一加密密钥传输到第一个管芯。 处理器可以接收第一加密密钥并且可以解密第一加密密钥以恢复秘密密钥，并且可以使用秘密密钥加密数据，以沿着卡外部的电连接进行通信。

公开(公告)号：US20090257590A1

公开(公告)日：2009-10-15

申请号：US12100400

申请日：2008-04-09

申请人： Zhimin Ding

发明人： Zhimin Ding

IPC分类号： H04L9/30

CPC分类号： H04L9/0825 ,  H04L9/0894 ,  H04L2209/80

摘要： A secure removable card has electrical connections for communication therewith. The card comprises a first integrated circuit die, with the first die including a processor. The card has a second integrated circuit die, with the second die including a non-volatile memory for storing a secret key, and a controller for controlling the operation of the non-volatile memory. A bus connects the first die with the second die. The processor can generate a key pair, having a public key portion and a private key portion upon power up, and transfers the public key portion across the bus to the second die. The controller can receive the public key and encrypt the secret key with the public key to generate a first encrypted key, and can transfer the first encrypted key across the bus to the first die. The processor can receive the first encrypted key and can decrypt the first encrypted key to recover the secret key, and can encrypt data with the secret key for communicating along the electrical connections external to the card.

摘要翻译： 安全的可拆卸卡具有用于与之通信的电连接。 该卡包括第一集成电路管芯，其中第一管芯包括处理器。 卡具有第二集成电路管芯，第二管芯包括用于存储秘密密钥的非易失性存储器，以及用于控制非易失性存储器的操作的控制器。 总线连接第一个模具和第二个模具。 处理器可以在上电时生成具有公钥部分和私钥部分的密钥对，并且将公共密钥部分跨越总线传送到第二管芯。 控制器可以接收公开密钥并用公开密钥加密秘密密钥，以产生第一个加密密钥，并且可以将总线上的第一加密密钥传输到第一个管芯。 处理器可以接收第一加密密钥并且可以解密第一加密密钥以恢复秘密密钥，并且可以使用秘密密钥加密数据，以沿着卡外部的电连接进行通信。

公开(公告)号：US20060218425A1

公开(公告)日：2006-09-28

申请号：US11345074

申请日：2006-01-31

申请人： Zhimin Ding ,  Shane Hollmer ,  Philip Barnett

发明人： Zhimin Ding ,  Shane Hollmer ,  Philip Barnett

IPC分类号： G06F1/00

CPC分类号： G06F21/79 ,  G06F21/6218 ,  G06F21/74

摘要： An integrated circuit device has a processing unit, a memory management unit, and a memory. The memory management unit is interposed between the memory and the processing unit for controlling access to the memory by the processing unit in one of three modes. In a first mode, called the system mode, the processing unit can access a system program stored in the memory for controlling the resources of the integrated circuit device. In a second mode, called the kernel mode, the processing unit can access an operating system program stored in the memory for controlling the of the integrated circuit device, limited by the system program. Finally in a third mode, called the user mode, the processing unit can access an application program stored in the memory for controlling the resources of the integrated circuit device, limited by the operating system program. In another aspect of the invention, when the processing unit accesses either the operating system program or the application program (herein: “non-system program”), the execution of the non-system program can cause a system interrupt causing program execution to revert to the system mode, but to a specified entry address of the system program, wherein after processing the system interrupt, operation returns to the non-system program in either the kernel mode or the user mode.

摘要翻译： 集成电路装置具有处理单元，存储器管理单元和存储器。 存储器管理单元插入在存储器和处理单元之间，用于以三种模式之一控制处理单元对存储器的访问。 在被称为系统模式的第一模式中，处理单元可以访问存储在存储器中的用于控制集成电路装置的资源的系统程序。 在称为内核模式的第二模式中，处理单元可以访问存储在存储器中的用于控制由系统程序限制的集成电路装置的操作系统程序。 最后，在称为用户模式的第三模式中，处理单元可以访问存储在存储器中的应用程序，用于控制由操作系统程序限制的集成电路设备的资源。 在本发明的另一方面，当处理单元访问操作系统程序或应用程序（这里为“非系统程序”）时，非系统程序的执行可能导致导致程序执行的系统中断恢复 到系统模式，但是指向系统程序的指定输入地址，其中在处理系统中断之后，操作以内核模式或用户模式返回到非系统程序。

公开(公告)号：US08392641B2

公开(公告)日：2013-03-05

申请号：US12785943

申请日：2010-05-24

申请人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig MacKenna

发明人： Pankaj Shrivastava ,  Gregory Goodhue ,  Ata Khan ,  Zhimin Ding ,  Craig MacKenna

IPC分类号： G06F13/24

CPC分类号： G06F9/4812 ,  G06F9/462 ,  G06F13/26 ,  Y02D10/14 ,  Y02D10/24

摘要： Aspects of the disclosure are directed to a system having a particularly-configured microcontroller. In one embodiment, the microcontroller includes the following: a processor; a processor data bus connected to the processor; a set of peripherals; a peripheral data bus connected to the peripherals; a peripheral bus bridge providing an interface between the processor data bus and the peripheral data base and including a plurality of special function register bank blocks that are internal to the microcontroller, each register bank block having a respective output; and a register bank block decoder circuit for decoding interrupts to provide a selection output for activation of one of the plurality of register bank blocks.

摘要翻译： 本公开的方面涉及具有特别配置的微控制器的系统。 在一个实施例中，微控制器包括以下：处理器; 连接到处理器的处理器数据总线; 一套外设; 连接到外围设备的外围数据总线; 提供处理器数据总线和外围数据库之间的接口的外围总线桥，并且包括微控制器内部的多个特殊功能寄存器组块，每个寄存器组块具有相应的输出; 以及寄存器块解码器电路，用于解码中断以提供用于激活所述多个寄存器组块之一的选择输出。