公开(公告)号：US10069000B2

公开(公告)日：2018-09-04

申请号：US15052460

申请日：2016-02-24

Applicant: ABB Technology AG

Inventor： Virgiliu Botan ,  Jan Vobecky ,  Karlheinz Stiegler

IPC: H01L29/744 ,  H01L29/66 ,  H01L29/74 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10

CPC classification number: H01L29/744 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/66363 ,  H01L29/74

Abstract: The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor wafer and a first electrode formed on a first main side of the wafer and a second electrode formed on a second main side of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer of a first conductivity type, and a first layer of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode.The wafer comprises an inner region wand an outer region surrounding the inner region. The drift layer has a thickness in the inner region greater or equal than a thickness in the outer region. A thickness of the first layer increases in a transition region between the inner region and the outer region from a thickness in the inner region to a maximum thickness in the outer region. The thickness of the first layer increases linearly over the transition region with a width of the transition region greater than 5 times a thickness of the first section of the first layer.

公开(公告)号：US09543305B2

公开(公告)日：2017-01-10

申请号：US15078602

申请日：2016-03-23

Applicant: ABB Technology AG

Inventor： Neophythos Lophitis ,  Florin Udrea ,  Umamaheswara Vemulapati ,  Lulian Nistor ,  Martin Arnold ,  Jan Vobecky ,  Munaf Rahimo

IPC: H01L29/66 ,  H01L27/102 ,  H01L29/87 ,  H01L29/417

CPC classification number: H01L27/1027 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/41716 ,  H01L29/7416 ,  H01L29/744 ,  H01L29/87

Abstract: A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w′), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w′) of each one of the two outer cathode layer regions next to a diode cell neighboring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.

Abstract translation: 提供了一种RC功率半导体，其包括多个二极管单元和多个GCT单元。 每个GCT单元包括具有至少三个阴极层区域的第一阴极层，其通过基底层彼此分离。 在与第一主面平行的平面上的正交投影中，每个阴极层区域是带状的和宽度（w，w'），其中二极管单元在横向方向上与至少一个 混合部分，其中在每个GCT单元中，与所述GCT单元相邻的二极管单元旁边的两个外部阴极层区域中的每一个的宽度（w'）小于所述GCT单元之间的任何中间阴极层区域的宽度（w） 该GCT电池中的两个外阴极层区域。

公开(公告)号：US20160284826A1

公开(公告)日：2016-09-29

申请号：US15052460

申请日：2016-02-24

Applicant: ABB Technology AG

Inventor： Virgiliu Botan ,  Jan Vobecky ,  Karlheinz Stiegler

IPC: H01L29/744 ,  H01L29/10 ,  H01L29/66 ,  H01L29/06

CPC classification number: H01L29/744 ,  H01L29/0638 ,  H01L29/0657 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/0839 ,  H01L29/102 ,  H01L29/1095 ,  H01L29/66363 ,  H01L29/74

Abstract: The invention relates to a bipolar non-punch-through power semiconductor device and a corresponding manufacturing method. The device comprises a semiconductor wafer and a first electrode formed on a first main side of the wafer and a second electrode formed on a second main side of the wafer opposite the first main side. The wafer comprises a pair of layers of different conductivity types, such as a drift layer of a first conductivity type, and a first layer of a second conductivity type arranged on the drift layer towards the first main side and contacting the first electrode.The wafer comprises an inner region wand an outer region surrounding the inner region. The drift layer has a thickness in the inner region greater or equal than a thickness in the outer region. A thickness of the first layer increases in a transition region between the inner region and the outer region from a thickness in the inner region to a maximum thickness in the outer region. The thickness of the first layer increases linearly over the transition region with a width of the transition region greater than 5 times a thickness of the first section of the first layer.

Abstract translation: 晶片包括内部区域和围绕内部区域的外部区域。 漂移层的内部区域的厚度大于或等于外部区域的厚度。 在内部区域和外部区域之间的过渡区域中，第一层的厚度从外部区域的内部区域的厚度增加到最大厚度。 第一层的厚度在过渡区域上线性增加，其中过渡区域的宽度大于第一层的第一部分的厚度的5倍。

公开(公告)号：US20140370665A1

公开(公告)日：2014-12-18

申请号：US14477229

申请日：2014-09-04

Applicant: ABB Technology AG

Inventor： Munaf RAHIMO ,  Chiara Corvasce ,  Jan Vobecky ,  Yoichi Otani

IPC: H01L29/66 ,  H01L21/283 ,  H01L21/324 ,  H01L21/225

CPC classification number: H01L29/66325 ,  H01L21/2251 ,  H01L21/283 ,  H01L21/324 ,  H01L29/0834 ,  H01L29/45 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/66333 ,  H01L29/66348 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/8613

Abstract: A method for manufacturing a power semiconductor device is disclosed which can include: providing a wafer of a first conductivity type; and applying on a second main side of the wafer at least one of a dopant of the first conductivity type for forming a layer of the first conductivity type and a dopant of a second conductivity type for forming a layer of the second conductivity type. A Titanium layer with a metal having a melting point above 1300° C. is then deposited on the second main side. The Titanium deposition layer is annealed so that simultaneously an intermetal compound layer is formed at the interface between the Titanium deposition layer and the wafer and the dopant is diffused into the wafer. A first metal electrode layer is created on the second main side.

Abstract translation: 公开了一种用于制造功率半导体器件的方法，其可以包括：提供第一导电类型的晶片; 以及在所述晶片的第二主侧上施加用于形成第一导电类型的第一导电类型的掺杂剂和用于形成第二导电类型的层的第二导电类型的掺杂剂中的至少一种。 然后将具有熔点高于1300℃的金属的钛层沉积在第二主侧上。 钛沉积层进行退火，从而在钛沉积层和晶片之间的界面处同时形成金属间化合物层，并且掺杂剂扩散到晶片中。 在第二主面上形成第一金属电极层。

公开(公告)号：US09385223B2

公开(公告)日：2016-07-05

申请号：US14748774

申请日：2015-06-24

Applicant: ABB Technology AG

Inventor： Munaf Rahimo ,  Martin Arnold ,  Jan Vobecky ,  Umamaheswara Vemulapati

IPC: H01L29/74 ,  H01L27/06 ,  H01L29/744

CPC classification number: H01L29/7416 ,  H01L27/0664 ,  H01L29/744

Abstract: A reverse-conducting power semiconductor device with a wafer has first and second main sides which are arranged opposite and parallel to each other. The device includes a plurality of diode cells and a plurality of gate commutated thyristors (GCT) cells. Each GCT cell includes layers of a first conductivity type (e.g., n-type) and a second conductivity type (e.g., p-type) between the first and second main sides. The device includes at least one mixed part in which diode anode layers of the diode cells alternate with first cathode layers of the GCT cells. In each diode cell, a diode buffer layer of the first conductivity type is arranged between the diode anode layer and a drift layer such that the diode buffer layer covers lateral sides of the diode anode layer from the first main side to a depth of approximately 90% of the thickness of the diode anode layer.

Abstract translation: 具有晶片的反向导电功率半导体器件具有彼此相对并平行布置的第一和第二主侧面。 该器件包括多个二极管单元和多个栅极换向晶闸管（GCT）单元。 每个GCT单元包括在第一和第二主侧之间的第一导电类型（例如，n型）和第二导电类型（例如，p型）的层。 该器件包括至少一个混合部分，其中二极管单元的二极管阳极层与GCT单元的第一阴极层交替。 在每个二极管单元中，第二导电类型的二极管缓冲层布置在二极管阳极层和漂移层之间，使得二极管缓冲层覆盖二极管阳极层的从第一主侧到大约90度的深度的侧面 二极管阳极层的厚度的百分比。

公开(公告)号：US08803192B2

公开(公告)日：2014-08-12

申请号：US13850732

申请日：2013-03-26

Applicant: ABB Technology AG

Inventor： Jan Vobecky ,  Munaf Rahimo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/74

CPC classification number: H01L29/74 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/102 ,  H01L29/66136 ,  H01L29/66363 ,  H01L29/8613

Abstract: An exemplary bipolar non-punch-through power semiconductor device includes a semiconductor wafer and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer has an inner region with a wafer thickness and a termination region that surrounds the inner region, such that the wafer thickness is reduced at least on the first main side with a negative bevel. The semiconductor wafer has at least a two-layer structure with layers of different conductivity types, which can include a drift layer of a first conductivity type, a first layer of a second conductivity type at a first layer depth and directly connected to the drift layer on the first main side and contacting the first electrical contact, and a second layer of the second conductivity type arranged in the termination region on the first main side up to a second layer depth.

Abstract translation: 示例性的双极非穿通功率半导体器件包括半导体晶片和第一主侧上的第一电触点和第二主侧上的第二电触点。 晶片具有晶片厚度的内部区域和围绕内部区域的终止区域，使得晶片厚度至少在第一主侧面上以负斜面减小。 半导体晶片具有至少具有不同导电类型的层的两层结构，其可以包括第一导电类型的漂移层，第一层深度处的第二导电类型的第一层并且直接连接到漂移层 在第一主侧并且接触第一电接触，以及布置在第一主侧上的端接区域中的第二导电类型的第二层直到第二层深度。

公开(公告)号：US20130207159A1

公开(公告)日：2013-08-15

申请号：US13850732

申请日：2013-03-26

Applicant: ABB TECHNOLOGY AG

Inventor： Jan Vobecky ,  Munaf Rahimo

IPC: H01L29/74 ,  H01L29/66

CPC classification number: H01L29/74 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0661 ,  H01L29/0834 ,  H01L29/102 ,  H01L29/66136 ,  H01L29/66363 ,  H01L29/8613

Abstract: An exemplary bipolar non-punch-through power semiconductor device includes a semiconductor wafer and a first electrical contact on a first main side and a second electrical contact on a second main side. The wafer has an inner region with a wafer thickness and a termination region that surrounds the inner region, such that the wafer thickness is reduced at least on the first main side with a negative bevel. The semiconductor wafer has at least a two-layer structure with layers of different conductivity types, which can include a drift layer of a first conductivity type, a first layer of a second conductivity type at a first layer depth and directly connected to the drift layer on the first main side and contacting the first electrical contact, and a second layer of the second conductivity type arranged in the termination region on the first main side up to a second layer depth.

Abstract translation: 示例性的双极非穿通功率半导体器件包括半导体晶片和第一主侧上的第一电触点和第二主侧上的第二电触点。 晶片具有晶片厚度的内部区域和围绕内部区域的终止区域，使得晶片厚度至少在第一主侧面上以负斜面减小。 半导体晶片具有至少具有不同导电类型的层的两层结构，其可以包括第一导电类型的漂移层，第一层深度处的第二导电类型的第一层并且直接连接到漂移层 在第一主侧并且接触第一电接触，以及布置在第一主侧上的端接区域中的第二导电类型的第二层直到第二层深度。

公开(公告)号：US20160284708A1

公开(公告)日：2016-09-29

申请号：US15078602

申请日：2016-03-23

Applicant: ABB Technology AG

Inventor： Neophythos Lophitis ,  Florin Udrea ,  Umamaheswara Vemulapati ,  lulian Nistor ,  Martin Arnold ,  Jan Vobecky ,  Munaf Rahimo

IPC: H01L27/102 ,  H01L29/417 ,  H01L29/87

CPC classification number: H01L27/1027 ,  H01L29/0696 ,  H01L29/0839 ,  H01L29/41716 ,  H01L29/7416 ,  H01L29/744 ,  H01L29/87

Abstract: A RC power semiconductor is provided which comprises a plurality of diode cells and a plurality of GCT cells. Each GCT cell comprises a first cathode layer with at least three cathode layer regions, which are separated from each other by a base layer. In orthogonal projection onto a plane parallel to the first main side each one of the cathode layer regions is strip-shaped and a width (w, w′), wherein the diode cells alternate with the GCT cells in a lateral direction in at least a mixed part, wherein in each GCT cell, the width (w′) of each one of the two outer cathode layer regions next to a diode cell neighbouring to that GCT cell is less than the width (w) of any intermediate cathode layer region between the two outer cathode layer regions in that GCT cell.

Abstract translation: 提供了一种RC功率半导体，其包括多个二极管单元和多个GCT单元。 每个GCT单元包括具有至少三个阴极层区域的第一阴极层，其通过基底层彼此分离。 在与第一主面平行的平面上的正交投影中，每个阴极层区域是带状的和宽度（w，w'），其中二极管单元在横向方向上与至少一个 混合部分，其中在每个GCT单元中，与所述GCT单元相邻的二极管单元旁边的两个外部阴极层区域中的每一个的宽度（w'）小于所述GCT单元之间的任何中间阴极层区域的宽度（w） 该GCT电池中的两个外阴极层区域。