公开(公告)号：US09949385B2

公开(公告)日：2018-04-17

申请号：US14790437

申请日：2015-07-02

Applicant: ABB TECHNOLOGY AG

Inventor： Samuel Hartmann ,  David Guillon ,  David Hajas ,  Markus Thut

IPC: H05K5/00 ,  H01L23/047 ,  H05K3/30 ,  H01R43/20 ,  H05K1/18 ,  H05K1/11 ,  H01L23/48 ,  H01R43/02 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498 ,  B23K20/10

CPC classification number: H05K5/0034 ,  B23K20/10 ,  H01L21/4853 ,  H01L23/047 ,  H01L23/3735 ,  H01L23/48 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49097 ,  H01L2224/49111 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01R43/0207 ,  H01R43/205 ,  H05K1/111 ,  H05K1/181 ,  H05K3/301 ,  H05K2203/0285 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor module includes a base plate, a substrate on the base plate and carrying at least one semiconductor chip, a housing attached to the base plate and at least partially enclosing the substrate, and at least one terminal having one end which protrudes from the housing and another end which has a terminal foot attached on a terminal pad of the metallization by means of ultrasonic welding. The housing has a protective wall which encloses the terminal and divides an interior space of the housing into an unprotected region and a protected region. The protective wall is formed such that a gap is formed between the substrate and the protective wall. The gap is designed to carry a fluid flow such that particles produced during the ultrasonic welding of the terminal foot to the terminal pad are prevented from penetrating into the protected region from the unprotected region.

公开(公告)号：US20160027762A1

公开(公告)日：2016-01-28

申请号：US14878466

申请日：2015-10-08

Applicant: ABB Technology AG

Inventor： Samuel Hartmann ,  Franc Dugal ,  Olle Ekwall ,  Erik Doré

IPC: H01L25/07 ,  H01L23/492 ,  H01L23/051

CPC classification number: H01L25/072 ,  H01L23/051 ,  H01L23/492 ,  H01L2224/48091 ,  H01L2924/13055 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A power semiconductor module includes a first main electrode, a second main electrode and a control terminal. The power semiconductor module includes controllable power semiconductor components arranged between the first main electrode and the second main electrode. At least some of the controllable power semiconductor components are arranged in a ring arrangement, wherein the controllable power semiconductor components of the ring arrangement are arranged at least approximately along a first circular line of the ring arrangement, and a control conductor track of the ring arrangement is arranged on the first main electrode, wherein the control conductor track runs at least approximately along a second circular line of the ring arrangement, and the second circular line runs concentrically relative to the first circular line.

Abstract translation: 功率半导体模块包括第一主电极，第二主电极和控制端子。 功率半导体模块包括布置在第一主电极和第二主电极之间的可控功率半导体部件。 至少一些可控功率半导体部件被布置成环形布置，其中环形布置的可控功率半导体部件至少大致沿着环形布置的第一圆形线布置，并且环形布置的控制导体轨道 布置在第一主电极上，其中控制导体轨道至少大致沿环形装置的第二圆形线延伸，并且第二圆形线相对于第一圆形线同心地延伸。

公开(公告)号：US09105489B2

公开(公告)日：2015-08-11

申请号：US13875733

申请日：2013-05-02

Applicant: ABB TECHNOLOGY AG

Inventor： Samuel Hartmann ,  Dominik Trüssel

IPC: H01L29/66 ,  H01L27/06 ,  H01L25/07 ,  H01L25/18

CPC classification number: H01L27/067 ,  H01L25/072 ,  H01L25/18 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A power semiconductor module includes a base plate and at least one pair of substrates mounted on the base plate. Multiple power semiconductors are mounted on each substrate. The power semiconductors are arranged on each substrate with a different number of power semiconductors along opposite edges thereof. The at least one pair of substrates is arranged on the base plate with the respective edges of the substrates provided with a lower number of power semiconductors facing towards each other.

Abstract translation: 功率半导体模块包括基板和安装在基板上的至少一对基板。 多功率半导体安装在每个基板上。 功率半导体布置在每个基板上，具有沿其相对边缘的不同数量的功率半导体。 至少一对基板布置在基板上，其中基板的相应边缘设置有朝向彼此面对的较少数量的功率半导体。

公开(公告)号：US09431376B2

公开(公告)日：2016-08-30

申请号：US14539422

申请日：2014-11-12

Applicant: ABB TECHNOLOGY AG

Inventor： Samuel Hartmann ,  Dominik Trüssel

IPC: H01L23/00 ,  H01L25/07

CPC classification number: H01L25/072 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48101 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/19107 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099

Abstract: Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.

Abstract translation: 示例性实施例提供用于安装多个功率晶体管的衬底。 衬底具有第一金属化，其上功率晶体管可由相关联的集电极或发射极安装在其上，并且在衬底上的至少一条线上延伸。 第二金属化在与第一金属化的至少一条线相邻的区域中延伸，用于连接到功率晶体管的其余发射极或集电极。 第三金属化允许连接到功率晶体管的栅极接触焊盘。 第三金属化包括栅极接触和可互连的至少两个栅极金属化区域。 栅极金属化区域布置成平行于至少一条线并且在至少一条线的纵向方向上间隔开。 提供至少一个栅极金属化区域作为通过第二金属化在基板上包围的栅极岛。