Abstract:
A power semiconductor module includes a base plate and at least one pair of substrates mounted on the base plate. Multiple power semiconductors are mounted on each substrate. The power semiconductors are arranged on each substrate with a different number of power semiconductors along opposite edges thereof. The at least one pair of substrates is arranged on the base plate with the respective edges of the substrates provided with a lower number of power semiconductors facing towards each other.
Abstract:
The present invention relates to a method of connecting two components by ultrasonic welding for producing a power semiconductor module, said method comprising the steps of: a) Aligning the components to be welded to form a welding interface; b) Aligning a welding tool to the aligned components; c) Removably arranging a trapping material at least partly encompassing the welding interface, whereby the trapping material is a foam; and d) Connecting the components by activating the welding tool. The method like described above provides an easy and cost-saving measure in order to prevent particle contamination when performing a welding process such as particularly an ultrasonic welding process sue to scattered particles.
Abstract:
The present invention relates to a method of connecting two components by ultrasonic welding for producing a power semiconductor module, said method comprising the steps of: a) Aligning the components to be welded to form a welding interface; b) Aligning a welding tool to the aligned components; c) Removably arranging a trapping material at least partly encompassing the welding interface, whereby the trapping material is a foam; and d) Connecting the components by activating the welding tool. The method like described above provides an easy and cost-saving measure in order to prevent particle contamination when performing a welding process such as particularly an ultrasonic welding process sue to scattered particles.
Abstract:
Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.
Abstract:
A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate. A metallic protection plate can be provided at an inner face of the top plate facing towards the base plate, wherein the material of the protection plate has a melting temperature higher than the melting temperature of the top plate.
Abstract:
A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate. A metallic protection plate can be provided at an inner face of the top plate facing towards the base plate, wherein the material of the protection plate has a melting temperature higher than the melting temperature of the top plate.
Abstract:
A method and arrangement are disclosed for electrically connecting a contact of a first substrate to a contact of a second substrate, whereby the first substrate is positioned relative the second substrate. The method includes providing the first substrate with its contact facing towards the second substrate, providing the second substrate with its contact facing away from the first substrate, bonding a bonding medium to the contact of the first substrate, bonding the bonding medium to the first substrate thereby forming a loop, electrically connecting the contact of the second substrate to the bonding medium, and providing the second substrate with the contact on a nose or tongue extending from an edge of the second substrate. The first substrate can be positioned below the second substrate, with a contact of the first substrate connected to a contact of the second substrate.