Power semiconductor module
    1.
    发明授权
    Power semiconductor module 有权
    功率半导体模块

    公开(公告)号:US09105489B2

    公开(公告)日:2015-08-11

    申请号:US13875733

    申请日:2013-05-02

    Abstract: A power semiconductor module includes a base plate and at least one pair of substrates mounted on the base plate. Multiple power semiconductors are mounted on each substrate. The power semiconductors are arranged on each substrate with a different number of power semiconductors along opposite edges thereof. The at least one pair of substrates is arranged on the base plate with the respective edges of the substrates provided with a lower number of power semiconductors facing towards each other.

    Abstract translation: 功率半导体模块包括基板和安装在基板上的至少一对基板。 多功率半导体安装在每个基板上。 功率半导体布置在每个基板上,具有沿其相对边缘的不同数量的功率半导体。 至少一对基板布置在基板上,其中基板的相应边缘设置有朝向彼此面对的较少数量的功率半导体。

    METHOD FOR ULTRASONIC WELDING WITH PARTICLES TRAPPING
    3.
    发明申请
    METHOD FOR ULTRASONIC WELDING WITH PARTICLES TRAPPING 有权
    用于超声波焊接的方法

    公开(公告)号:US20160193678A1

    公开(公告)日:2016-07-07

    申请号:US15067779

    申请日:2016-03-11

    CPC classification number: B23K1/06 B23K20/10 B23K20/26 B29C35/0261

    Abstract: The present invention relates to a method of connecting two components by ultrasonic welding for producing a power semiconductor module, said method comprising the steps of: a) Aligning the components to be welded to form a welding interface; b) Aligning a welding tool to the aligned components; c) Removably arranging a trapping material at least partly encompassing the welding interface, whereby the trapping material is a foam; and d) Connecting the components by activating the welding tool. The method like described above provides an easy and cost-saving measure in order to prevent particle contamination when performing a welding process such as particularly an ultrasonic welding process sue to scattered particles.

    Abstract translation: 本发明涉及一种通过超声波焊接连接两个部件以产生功率半导体模块的方法,所述方法包括以下步骤:a)对准被焊接部件以形成焊接界面; b)将焊接工具对准对齐的部件; c)可移除地布置至少部分地包围焊接界面的捕集材料,由此捕获材料是泡沫; 和d)通过激活焊接工具连接组件。 上述方法提供了一种简单且成本节约的措施,以便在执行诸如特别是对散射颗粒的超声波焊接工艺的焊接过程时防止颗粒污染。

    Substrate for mounting multiple power transistors thereon and power semiconductor module
    4.
    发明授权
    Substrate for mounting multiple power transistors thereon and power semiconductor module 有权
    用于在其上安装多个功率晶体管的基板和功率半导体模块

    公开(公告)号:US09431376B2

    公开(公告)日:2016-08-30

    申请号:US14539422

    申请日:2014-11-12

    Abstract: Exemplary embodiments provide a substrate for mounting multiple power transistors. The substrate has a first metallization on which the power transistors are mountable with an associated collector or emitter, and which extends in at least one line on the substrate. A second metallization extends in an area next to the at least one line of the first metallization, for connection to the remaining ones of the emitters or collectors of the power transistors. A third metallization allows connection to gate contact pads of the power transistors. The third metallization includes a gate contact and at least two gate metallization areas, which are interconnectable. The gate metallization areas are arranged in parallel to the at least one line and spaced apart in a longitudinal direction of the at least one line. At least one gate metallization area is provided as a gate island surrounded on the substrate by the second metallization.

    Abstract translation: 示例性实施例提供用于安装多个功率晶体管的衬底。 衬底具有第一金属化,其上功率晶体管可由相关联的集电极或发射极安装在其上,并且在衬底上的至少一条线上延伸。 第二金属化在与第一金属化的至少一条线相邻的区域中延伸,用于连接到功率晶体管的其余发射极或集电极。 第三金属化允许连接到功率晶体管的栅极接触焊盘。 第三金属化包括栅极接触和可互连的至少两个栅极金属化区域。 栅极金属化区域布置成平行于至少一条线并且在至少一条线的纵向方向上间隔开。 提供至少一个栅极金属化区域作为通过第二金属化在基板上包围的栅极岛。

    Power semiconductor module and power semiconductor module assembly with multiple power semiconductor modules
    5.
    发明授权
    Power semiconductor module and power semiconductor module assembly with multiple power semiconductor modules 有权
    功率半导体模块和功率半导体模块组合,具有多个功率半导体模块

    公开(公告)号:US09035447B2

    公开(公告)日:2015-05-19

    申请号:US14257397

    申请日:2014-04-21

    Abstract: A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate. A metallic protection plate can be provided at an inner face of the top plate facing towards the base plate, wherein the material of the protection plate has a melting temperature higher than the melting temperature of the top plate.

    Abstract translation: 公开了一种功率半导体模块和功率半导体模块组件,其包括多个功率半导体模块。 功率半导体模块包括导电基板,导电顶板,平行于基板并与基板间隔开,至少一个功率半导体器件,其设置在基板上形成的空间中 在基板和顶板之间,以及至少一个压扣,其布置在形成在基板和顶板之间的空间中,以提供半导体器件和顶板之间的接触。 金属保护板可以设置在顶板的面向底板的内表面处,其中保护板的材料的熔化温度高于顶板的熔化温度。

    POWER SEMICONDUCTOR MODULE AND POWER SEMICONDUCTOR MODULE ASSEMBLY WITH MULTIPLE POWER SEMICONDUCTOR MODULES
    6.
    发明申请
    POWER SEMICONDUCTOR MODULE AND POWER SEMICONDUCTOR MODULE ASSEMBLY WITH MULTIPLE POWER SEMICONDUCTOR MODULES 有权
    功率半导体模块和功率半导体模块组件与多功率半导体模块

    公开(公告)号:US20140225245A1

    公开(公告)日:2014-08-14

    申请号:US14257397

    申请日:2014-04-21

    Abstract: A power semiconductor module and a power semiconductor module assembly, which includes a plurality of power semiconductor modules, are disclosed. The power semiconductor module includes an electrically conducting base plate, an electrically conducting top plate, arranged in parallel to the base plate and spaced apart from the base plate, at least one power semiconductor device, which is arranged on the base plate in a space formed between the base plate and the top plate, and at least one presspin, which is arranged in the space formed between the base plate and the top plate to provide contact between the semiconductor device and the top plate. A metallic protection plate can be provided at an inner face of the top plate facing towards the base plate, wherein the material of the protection plate has a melting temperature higher than the melting temperature of the top plate.

    Abstract translation: 公开了一种功率半导体模块和功率半导体模块组件,其包括多个功率半导体模块。 功率半导体模块包括导电基板,导电顶板,平行于基板并与基板间隔开,至少一个功率半导体器件,其设置在基板上形成的空间中 在基板和顶板之间,以及至少一个压扣,其布置在形成在基板和顶板之间的空间中,以提供半导体器件和顶板之间的接触。 金属保护板可以设置在顶板的面向底板的内表面处,其中保护板的材料的熔化温度高于顶板的熔化温度。

    METHOD FOR ELECTRICALLY CONNECTING VERTICALLY POSITIONED SUBSTRATES
    7.
    发明申请
    METHOD FOR ELECTRICALLY CONNECTING VERTICALLY POSITIONED SUBSTRATES 审中-公开
    用于电气连接垂直定位的基板的方法

    公开(公告)号:US20140021640A1

    公开(公告)日:2014-01-23

    申请号:US13937546

    申请日:2013-07-09

    Abstract: A method and arrangement are disclosed for electrically connecting a contact of a first substrate to a contact of a second substrate, whereby the first substrate is positioned relative the second substrate. The method includes providing the first substrate with its contact facing towards the second substrate, providing the second substrate with its contact facing away from the first substrate, bonding a bonding medium to the contact of the first substrate, bonding the bonding medium to the first substrate thereby forming a loop, electrically connecting the contact of the second substrate to the bonding medium, and providing the second substrate with the contact on a nose or tongue extending from an edge of the second substrate. The first substrate can be positioned below the second substrate, with a contact of the first substrate connected to a contact of the second substrate.

    Abstract translation: 公开了一种用于将第一基板的触点电连接到第二基板的触点的方法和装置,由此第一基板相对于第二基板定位。 该方法包括提供其第一基底的接触面朝向第二基底,使第二基底的接触面远离第一基底,将接合介质粘合到第一基底的接触面上,将接合介质粘合到第一基底 从而形成环路,将第二基板的接触电连接到接合介质,以及将第二基板提供在从第二基板的边缘延伸的鼻或舌上的接触。 第一基板可以位于第二基板的下方,第一基板的接触连接到第二基板的接触。

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