公开(公告)号：US20150026407A1

公开(公告)日：2015-01-22

申请号：US13946125

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Edward J. McLellan ,  Sudha Thiruvengadam ,  Douglas R. Beard ,  Carl D. Dietz ,  Stephen V. Kosonocky

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3206 ,  G06F1/3275 ,  G06F12/0804 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14

Abstract: As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.

Abstract translation: 当处理器进入选择的低功耗模式时，通过将存储在高速缓存中的数据写入存储器层次结构的其他级别来缓冲数据。 高速缓存的刷新允许减小高速缓存的大小，而不会在将减少的高速缓存位置处的数据写入存储器层次结构方面带来额外的性能损失。 因此，当高速缓存退出所选择的低功率模式时，通过将高速缓存的路数设置为最小数量，将其设置为最小大小。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。

公开(公告)号：US09021207B2

公开(公告)日：2015-04-28

申请号：US13723093

申请日：2012-12-20

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Edward J. McLellan ,  Paul Keltcher ,  Srilatha Manne ,  Richard E. Klass ,  James M. O'Connor

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  Y02D10/13

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract translation: 响应处理器核心退出低功率状态，将高速缓存设置为最小大小，使得少于所有高速缓存的条目可用于存储数据，从而减少高速缓存的功耗。 随着时间的推移，可以增加高速缓存的大小以考虑到处理器活动的增加，从而确保处理效率不受减小的高速缓存大小的显着影响。 在一些实施例中，基于所测量的处理器性能度量（例如高速缓存的逐出速率）来增加高速缓存大小。 在一些实施例中，高速缓存大小以规则的间隔增加，直到达到最大大小。

公开(公告)号：US09575553B2

公开(公告)日：2017-02-21

申请号：US14576924

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Seng Oon Toh ,  Edward J. McLellan ,  Stephen V. Kosonocky ,  Michael Leonard Golden ,  Samuel D. Naffziger

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract translation: 处理器在处理器处采用一组复制路径来确定处理器的工作频率和电压。 复制路径各自表示处理器的功能模块处的一个或多个电路路径。 复制路径上的延迟被归一化以增加复制路径准确地表示功能模块的电路路径的行为的可能性。 在归一化之后，通过在每个复制路径处改变复制路径的输出节点处的延迟，直到在复制路径的输出节点处的信号与在复制路径的延迟表示之间检测到不匹配来生成延迟值的分布 信号。 然后可以基于复制路径上的参考电压的变化来调整所得到的延迟值分布，以考虑由参考电压变化导致的电位分布误差。

公开(公告)号：US20160179186A1

公开(公告)日：2016-06-23

申请号：US14576924

申请日：2014-12-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Seng Oon Toh ,  Edward J. McLellan ,  Stephen V. Kosonocky ,  Michael Leonard Golden ,  Samuel D. Naffziger

IPC: G06F1/32

CPC classification number: G06F1/3296 ,  G06F1/04 ,  G06F1/3206 ,  G06F1/324 ,  Y02D10/126 ,  Y02D10/172

Abstract: A processor employs a set of replica paths at a processor to determine an operating frequency and voltage for the processor. The replica paths each represent one or more circuit paths at a functional module of the processor. The delays at the replica paths are normalized to increase the likelihood that the replica paths accurately represent the behavior of the circuit paths of the functional module. After normalization, a distribution of delay values is generated by varying, at each replica path, the delay at an output node of the replica path until a mismatch is detected between a signal at the output node of the replica path and the delayed representation of the signal. The resulting distribution of delay values can then be adjusted based on variations in reference voltages at the replica paths to account for potential distribution errors resulting from the reference voltage variations.

Abstract translation: 处理器在处理器处采用一组复制路径来确定处理器的工作频率和电压。 复制路径各自表示处理器的功能模块处的一个或多个电路路径。 复制路径上的延迟被归一化以增加复制路径准确地表示功能模块的电路路径的行为的可能性。 在归一化之后，通过在每个复制路径处改变复制路径的输出节点处的延迟，直到在复制路径的输出节点处的信号与在复制路径的延迟表示之间检测到不匹配来生成延迟值的分布 信号。 然后可以基于复制路径上的参考电压的变化来调整所得到的延迟值分布，以考虑由参考电压变化导致的电位分布误差。

公开(公告)号：US20140181410A1

公开(公告)日：2014-06-26

申请号：US13723093

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John Kalamatianos ,  Edward J. McLellan ,  Paul Keltcher ,  Srilatha Manne ,  Richard E. Klass ,  James M. O'Connor

IPC: G06F12/12

CPC classification number: G06F12/121 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864 ,  G06F2212/1028 ,  G06F2212/502 ,  G06F2212/601 ,  Y02D10/13

Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.

Abstract translation: 响应处理器核心退出低功率状态，将高速缓存设置为最小大小，使得少于所有高速缓存的条目可用于存储数据，从而减少高速缓存的功耗。 随着时间的推移，可以增加高速缓存的大小以考虑到处理器活动的增加，从而确保处理效率不受减小的高速缓存大小的显着影响。 在一些实施例中，基于所测量的处理器性能度量（例如高速缓存的逐出速率）来增加高速缓存大小。 在一些实施例中，高速缓存大小以规则的间隔增加，直到达到最大大小。

公开(公告)号：US20150026406A1

公开(公告)日：2015-01-22

申请号：US13946120

申请日：2013-07-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Edward J. McLellan ,  Sudha Thiruvengadam ,  Douglas R. Beard ,  Carl D. Dietz ,  Stephen V. Kosonocky

IPC: G06F12/08

CPC classification number: G06F12/0864 ,  G06F1/3275 ,  G06F1/3287 ,  G06F9/4418 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache.

Abstract translation: 通过各种方式来调整处理系统的高速缓存的大小，使得每组高速缓存具有相同数量的方式。 高速缓存是集合关联缓存，其中每个集合包括多种方式。 响应于处理系统处的定义的事件，高速缓存控制器改变每组高速缓存的路数。 例如，响应于处理器核心指示其进入减少活动的时段，高速缓存控制器可以减少高速缓存的每组中可用的路数。