公开(公告)号：US20220188024A1

公开(公告)日：2022-06-16

申请号：US17118034

申请日：2020-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F3/06

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.

公开(公告)号：US20210201986A1

公开(公告)日：2021-07-01

申请号：US16730086

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Naveen Davanam ,  Oswin E. Housty

IPC: G11C11/406 ,  G06F12/02 ,  G06F1/3234 ,  G06F13/16 ,  G06F13/40

Abstract: Methods for reducing boot time of a system-on-a-chip (SOC) by reducing double data rate (DDR) memory training and memory context restore. Dynamic random access memory (DRAM) controller and DDR physical interface (PHY) settings are stored into a non-volatile memory and the DRAM controller and DDR PHY are powered down. On system resume, a basic input/output system restores the DRAM controller and DDR PHY settings from non-volatile memory, and finalizes the DRAM controller and DDR PHY settings for operation with the SOC. Reducing the boot time of the SOC by reducing DDR training includes setting DRAMs into self-refresh mode, and programing a self-refresh state machine memory operation (MOP) array to exit self-refresh mode and update any DRAM device state for the target power management state. The DRAM device is reset, and the self-refresh state machine MOP array reinitializes the DRAM device state for the target power management state.

公开(公告)号：US10042700B2

公开(公告)日：2018-08-07

申请号：US15168045

申请日：2016-05-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G11C29/00 ,  G06F11/10 ,  G06F3/06 ,  G11C29/52

Abstract: A post-package repair system includes a memory channel controller, a first error counter, a scrubber, and a data processor. The memory channel controller converts data access requests to corresponding memory accesses, and provides returned data to the host interface in response to responses received from a memory interface, wherein the responses comprise returned data and a plurality of error correcting code (ECC) bits. The first error counter counts errors in the returned data, and provides a control signal in response to reaching a predetermined state. The scrubber controls the memory channel controller to read data sequentially and periodically from a plurality of addresses of a memory system, and in response to detecting a correctable error, to rewrite corrected data. The data processor is responsive to the control signal to perform a post package repair operation with the memory system in response to the control signal.

公开(公告)号：US20180113648A1

公开(公告)日：2018-04-26

申请号：US15299994

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Scott P. Murphy ,  James R. Magro ,  Paramjit K. Lubana

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F13/16

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.

公开(公告)号：US20150221358A1

公开(公告)日：2015-08-06

申请号：US14171362

申请日：2014-02-03

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kevin M. Brandl

IPC: G11C11/408 ,  G06F13/16 ,  G11C11/406

CPC classification number: G11C11/4087 ,  G06F13/1636 ,  G06F13/1642 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4085

Abstract: In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.

Abstract translation: 在一种形式中，存储器包括存储体，页面缓冲器和访问电路。 存储体具有在多行和多列的交叉处具有易失性存储单元的多行和多列。 页面缓冲器耦合到多个列，并且存储多行中所选择的一行的内容。 访问电路响应相邻命令和行地址来对行地址执行预定操作，并且刷新与行地址相邻的第一和第二地址。 在另一形式中，存储器控制器适于与这样的存储器接口，以基于在预定时间窗口中发送到行的激活命令的数量来选择正常命令或相邻命令。

公开(公告)号：US20240220379A1

公开(公告)日：2024-07-04

申请号：US18091163

申请日：2022-12-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F11/20 ,  G06F11/14

CPC classification number: G06F11/2094 ,  G06F11/1402 ,  G06F2201/805

Abstract: A memory controller includes a command queue, an arbiter, and a controller. The controller is responsive to a repair signal for migrating data from a failing region of a memory to a buffer, generating at least one command to perform a post-package repair operation of the failing region, and migrating the data from the buffer to a substitute region of the memory. The controller migrates the data to and from the buffer by providing migration read requests and migration write requests, respectively, to the command queue. The arbiter uses the plurality of arbitration rules for both the read migration requests and the write migration requests, and the read access requests and the write access requests.

公开(公告)号：US11474746B2

公开(公告)日：2022-10-18

申请号：US17118034

申请日：2020-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G06F3/06

Abstract: A memory controller interfaces with a dynamic random access memory (DRAM). The memory controller selectively places memory commands in a memory interface queue and transmits the memory commands from the memory interface queue to a memory channel coupled to at least one dynamic random access memory (DRAM). An activate counter is maintained related to a number of activate commands sent over the memory channel to a memory region of the DRAM. In response to the activate counter being at or above a designated threshold, an arbiter is signaled that a refresh command should be sent to the memory region. In response to a designated condition, a value of the activate counter is adjusted by a total number based on a first fixed number and second varying number selected with one of random selection and pseudo-random selection.

公开(公告)号：US09965222B1

公开(公告)日：2018-05-08

申请号：US15299994

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Scott P. Murphy ,  James R. Magro ,  Paramjit K. Lubana

IPC: G06F3/06 ,  G06F11/07

CPC classification number: G06F11/073 ,  G06F11/0793 ,  G06F13/16

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor includes a memory controller coupled to the memory channel and is adapted to access at least one rank of double data rate memory. The memory controller includes a command queue for storing received memory access requests, and an arbiter for picking memory access requests from the command queue, and then providing the memory access requests to the memory channel. The memory access requests are selected based on predetermined criteria, and in response to a mode register access request to quiesce pending operations. Additionally, the memory controller includes a mode register access controller that in response to the mode register access request, generates at least one corresponding mode register set command to a memory bus. The memory controller then relinquishes control of the memory bus to the arbiter thereafter.

公开(公告)号：US20180019006A1

公开(公告)日：2018-01-18

申请号：US15211887

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl ,  Thomas Hamilton ,  Hideki Kanayama ,  Kedarnath Balakrishnan ,  James R. Magro ,  Guanhao Shen ,  Mark Fowler

IPC: G11C7/10 ,  G11C11/408

CPC classification number: G11C7/1063 ,  G06F12/1018 ,  G06F2212/1041 ,  G11C7/10 ,  G11C7/1072 ,  G11C11/408

Abstract: A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

公开(公告)号：US09293188B2

公开(公告)日：2016-03-22

申请号：US14171362

申请日：2014-02-03

Applicant: Advanced Micro Devices, Inc.

Inventor： Kevin M. Brandl

IPC: G11C7/22 ,  G11C11/408 ,  G11C11/406 ,  G06F13/16 ,  G11C7/10

CPC classification number: G11C11/4087 ,  G06F13/1636 ,  G06F13/1642 ,  G06F13/1668 ,  G11C7/1072 ,  G11C7/22 ,  G11C7/222 ,  G11C11/406 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4085

Abstract: In one form, a memory includes a memory bank, a page buffer, and an access circuit. The memory bank has a plurality of rows and a plurality of columns with volatile memory cells at intersections of the plurality of row and the plurality of columns. The page buffer is coupled to the plurality of columns and stores contents of a selected one of the plurality of rows. The access circuit is responsive to an adjacent command and a row address to perform a predetermined operation on the row address, and to refresh first and second addresses adjacent to the row address. In another form, a memory controller is adapted to interface with such a memory to select either a normal command or an adjacent command based on a number of activate commands sent to the row in a predetermined time window.

Abstract translation: 在一种形式中，存储器包括存储体，页面缓冲器和访问电路。 存储体具有在多行和多列的交叉处具有易失性存储单元的多行和多列。 页面缓冲器耦合到多个列，并且存储多行中所选择的一行的内容。 访问电路响应相邻命令和行地址来对行地址执行预定操作，并且刷新与行地址相邻的第一和第二地址。 在另一形式中，存储器控制器适于与这样的存储器接口，以基于在预定时间窗口中发送到行的激活命令的数量来选择正常命令或相邻命令。