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公开(公告)号：US20170279444A1
公开(公告)日：2017-09-28
申请号：US15216498
申请日：2016-07-21
Applicant: Analog Devices Global
IPC: H03K17/567 , H02P27/06 , H02M7/217 , H01L27/06 , H02M7/537
CPC classification number: H03K17/567 , H01L27/0623 , H02M7/217 , H02M7/537 , H02P27/06 , H03K17/06 , H03K2017/066
Abstract: A combined isolator and power switch is disclosed. Such devices are useful in isolating low voltage components such as control compilers from motors or generators working at high voltages. The combined isolator and power switch includes circuits to transfer internal power from its low voltage side to the switch driver circuits on the high voltage side. The combined isolator and switch is compact and easy to use.
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公开(公告)号：US09698594B2
公开(公告)日：2017-07-04
申请号：US14937771
申请日：2015-11-10
Applicant: Analog Devices Global
Inventor： Edward John Coyne
IPC: H02H9/04 , H01L27/02 , H01L27/06 , H01L29/808 , H01L23/58
CPC classification number: H02H9/046 , H01L23/58 , H01L27/0248 , H01L27/0259 , H01L27/0266 , H01L27/0623 , H01L29/0653 , H01L29/0688 , H01L29/1066 , H01L29/8083
Abstract: Components can be damaged if they are exposed to excess voltages. A device is disclosed herein which can be placed in series with a component and a node that may be exposed to high voltages. If the voltage becomes too high, the device can autonomously switch into a relatively high impedance state, thereby protecting the other components.
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公开(公告)号：US09484739B2
公开(公告)日：2016-11-01
申请号：US14496839
申请日：2014-09-25
Applicant: ANALOG DEVICES GLOBAL
Inventor： Edward John Coyne , John Twomey , Seamus P. Whiston , David J. Clarke , Donal P. McAuliffe , William Allan Lane , Stephen Denis Heffernan , Brian A. Moane , Brian Michael Sweeney , Patrick Martin McGuinness
CPC classification number: H02H9/044 , H01L27/0259 , H02H7/16
Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.
Abstract translation: 提供一种保护装置，其展现了一纳秒或更少的转动时间。 这样一种器件为集成电路提供了防止静电放电事件的增强保护。 这反过来又降低了使用设备故障的风险。 保护装置可以包括连接在要保护的节点和放电路径之间的双极晶体管结构。
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公开(公告)号：US20190361071A1
公开(公告)日：2019-11-28
申请号：US16513562
申请日：2019-07-16
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US10181719B2
公开(公告)日：2019-01-15
申请号：US14658779
申请日：2015-03-16
Applicant: Analog Devices Global
Inventor： Edward John Coyne
Abstract: A protection device is provided that is placed in series connection between an input or signal node and a node to be protected. If the node to be protected is a relatively high impedance node, such as the gate of a MOSFET, then the protection device need not carry much current. This enables it to be built to be very fast. This enables it to respond rapidly to an overvoltage event so as to protect the circuit connected to the node to be protected. The protection device may be used in conjunction with other protection cells that offer greater current carrying capability and controllable trigger voltages, but which are intrinsically slower acting.
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Patent Agency Ranking
公开(公告)号：US20160133701A1
公开(公告)日：2016-05-12
申请号：US14539593
申请日：2014-11-12
Applicant: ANALOG DEVICES GLOBAL
Inventor： Breandan Pol Og O hAnnaidh , Seamus Paul Whiston , Edward John Coyne , William Allan Lane , Donal Peter McAuliffe
IPC: H01L29/06 , H01L29/423 , H01L29/417 , H01L29/78 , H01L29/66
CPC classification number: H01L29/0692 , H01L29/0847 , H01L29/402 , H01L29/41758 , H01L29/42376 , H01L29/4238 , H01L29/66568 , H01L29/78 , H01L29/7835 , H01L29/808
Abstract: A transistor is provided in which an elongate drain region has end portions formed in parts of the transistor where features of the transistor structure have been modified or omitted. These structures lessen the current flow or electric field gradients at the end portions of the drain. This provides a transistor that has improved on-state breakdown performance without sacrificing off state breakdown performance.
Abstract translation: 提供一种晶体管，其中细长的漏极区域具有形成在晶体管的部分中的端部，其晶体管结构的特征已被修改或省略。 这些结构减少了漏极端部处的电流或电场梯度。 这提供了具有改善的导通状态击穿性能而不牺牲关断状态击穿性能的晶体管。
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公开(公告)号：US09202934B2
公开(公告)日：2015-12-01
申请号：US14055738
申请日：2013-10-16
Applicant: ANALOG DEVICES GLOBAL
Inventor： Edward John Coyne
IPC: H01L29/80 , H01L31/112 , H01L29/808 , H01L29/66 , H01L29/08 , H01L29/10
CPC classification number: H01L29/808 , H01L29/0843 , H01L29/1058 , H01L29/66893 , H01L29/66901
Abstract: A method of forming a junction field effect transistor, the transistor comprising: a back gate; a channel; a top gate; a drain and a source in current flow with the channel; wherein the method comprises selecting a first channel dimension between the top gate and the back gate such that a significant current flow path in the channel occurs in a region of relatively low electric field strength.
Abstract translation: 一种形成结型场效应晶体管的方法，所述晶体管包括：背栅极; 一个渠道 顶门 电流与通道的漏极和源极; 其中所述方法包括选择所述顶栅极和所述后栅极之间的第一沟道尺寸，使得所述沟道中的有效电流流动路径发生在相对低的电场强度的区域中。
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公开(公告)号：US20210088580A1
公开(公告)日：2021-03-25
申请号：US17062225
申请日：2020-10-02
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US10794950B2
公开(公告)日：2020-10-06
申请号：US16513562
申请日：2019-07-16
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US10365322B2
公开(公告)日：2019-07-30
申请号：US15490584
申请日：2017-04-18
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
IPC: G01R31/28
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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