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公开(公告)号：US20190361071A1
公开(公告)日：2019-11-28
申请号：US16513562
申请日：2019-07-16
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US20170317070A1
公开(公告)日：2017-11-02
申请号：US15142453
申请日：2016-04-29
Applicant: Analog Devices Global
Inventor： Javier Alejandro Salcedo , David J. Clarke
IPC: H01L27/02 , H04B1/40 , H01L23/532 , H01L23/552 , H01L23/00 , H01L25/18 , H01L27/06 , H01L29/06 , H01L29/73 , H01L23/495 , H01L23/528 , H01L23/522
CPC classification number: H01L27/0262 , H01L23/49541 , H01L23/5228 , H01L23/528 , H01L23/53271 , H01L23/552 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/18 , H01L27/0255 , H01L27/0647 , H01L29/0649 , H01L29/0684 , H01L29/0692 , H01L29/73 , H01L29/861 , H01L2224/32145 , H01L2224/48091 , H01L2224/48101 , H01L2224/48106 , H01L2224/48145 , H01L2224/48247 , H01L2224/49105 , H01L2224/49171 , H01L2224/73265 , H01L2924/1203 , H01L2924/12036 , H01L2924/1207 , H01L2924/13034 , H01L2924/1305 , H01L2924/13091 , H01L2924/1426 , H01L2924/3025 , H04B1/40 , H01L2924/00
Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.
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公开(公告)号：US20200158771A1
公开(公告)日：2020-05-21
申请号：US16743878
申请日：2020-01-15
Applicant: Analog Devices Global
Inventor： Alan J. O'Donnell , David Aherne , Javier Alejandro Salcedo , David J. Clarke , John A. Cleary , Patrick Martin McGuinness , Albert C. O'Grady
Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.
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公开(公告)号：US20160094026A1
公开(公告)日：2016-03-31
申请号：US14496839
申请日：2014-09-25
Applicant: ANALOG DEVICES GLOBAL
Inventor： Edward John Coyne , John Twomey , Seamus P. Whiston , David J. Clarke , Donal P. McAuliffe , William Allan Lane , Stephen Denis Heffernan , Brian A. Moane , Brian Michael Sweeney , Patrick Martin McGuinness
CPC classification number: H02H9/044 , H01L27/0259 , H02H7/16
Abstract: A protection device is provided that exhibits a turn on time of order of one nanosecond or less. Such a device provides enhanced protection for integrated circuits against electrostatic discharge events. This in turn reduces the risk of device failure in use. The protection device can include a bipolar transistor structure connected between a node to be protected and a discharge path.
Abstract translation: 提供一种保护装置，其展现了一纳秒或更少的转动时间。 这样一种器件为集成电路提供了防止静电放电事件的增强保护。 这反过来又降低了使用设备故障的风险。 保护装置可以包括连接在要保护的节点和放电路径之间的双极晶体管结构。
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公开(公告)号：US11193967B2
公开(公告)日：2021-12-07
申请号：US16743878
申请日：2020-01-15
Applicant: Analog Devices Global
Inventor： Alan J. O'Donnell , David Aherne , Javier Alejandro Salcedo , David J. Clarke , John A. Cleary , Patrick Martin McGuinness , Albert C. O'Grady
IPC: G01R31/00 , G08B21/18 , H02H1/00 , H02H9/04 , H02H3/20 , H05K1/02 , H02H9/00 , H01L27/02 , H02H3/04
Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.
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Patent Agency Ranking
公开(公告)号：US20210088580A1
公开(公告)日：2021-03-25
申请号：US17062225
申请日：2020-10-02
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US10794950B2
公开(公告)日：2020-10-06
申请号：US16513562
申请日：2019-07-16
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US10557881B2
公开(公告)日：2020-02-11
申请号：US15801132
申请日：2017-11-01
Applicant: Analog Devices Global
Inventor： Alan J. O'Donnell , David Aherne , Javier Alejandro Salcedo , David J. Clarke , John A. Cleary , Patrick Martin McGuinness , Albert C. O'Grady
Abstract: Aspects of this disclosure relate to detecting and recording information associated with electrical overstress (EOS) events, such as electrostatic discharge (ESD) events. For example, in one embodiment, an apparatus includes an electrical overstress protection device, a detection circuit configured to detect an occurrence of the EOS event, and a memory configured to store information indicative of the EOS event.
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公开(公告)号：US10365322B2
公开(公告)日：2019-07-30
申请号：US15490584
申请日：2017-04-18
Applicant: Analog Devices Global
Inventor： Edward John Coyne , Alan J. O'Donnell , Shaun Bradley , David Aherne , David Boland , Thomas G. O'Dwyer , Colm Patrick Heffernan , Kevin B. Manning , Mark Forde , David J. Clarke , Michael A. Looby
IPC: G01R31/28
Abstract: The disclosed technology generally relates to integrated circuit devices with wear out monitoring capability. An integrated circuit device includes a wear-out monitor device configured to record an indication of wear-out of a core circuit separated from the wear-out monitor device, wherein the indication is associated with localized diffusion of a diffusant within the wear-out monitor device in response to a wear-out stress that causes the wear-out of the core circuit.
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公开(公告)号：US09831233B2
公开(公告)日：2017-11-28
申请号：US15142453
申请日：2016-04-29
Applicant: Analog Devices Global
Inventor： Javier Alejandro Salcedo , David J. Clarke
IPC: H01L21/02 , H01L27/02 , H01L29/06 , H01L23/528 , H01L23/552 , H01L23/522 , H01L23/532 , H01L29/73 , H01L27/06 , H04B1/40 , H01L25/18 , H01L23/495 , H01L23/00
CPC classification number: H01L27/0262 , H01L23/49541 , H01L23/5228 , H01L23/528 , H01L23/53271 , H01L23/552 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/18 , H01L27/0255 , H01L27/0647 , H01L29/0649 , H01L29/0684 , H01L29/0692 , H01L29/73 , H01L29/861 , H01L2224/32145 , H01L2224/48091 , H01L2224/48101 , H01L2224/48106 , H01L2224/48145 , H01L2224/48247 , H01L2224/49105 , H01L2224/49171 , H01L2224/73265 , H01L2924/1203 , H01L2924/12036 , H01L2924/1207 , H01L2924/13034 , H01L2924/1305 , H01L2924/13091 , H01L2924/1426 , H01L2924/3025 , H04B1/40 , H01L2924/00
Abstract: An integrated circuit device for protecting circuits from transient electrical events is disclosed. An integrated circuit device includes a semiconductor substrate having formed therein a bidirectional semiconductor rectifier (SCR) having a cathode/anode electrically connected to a first terminal and an anode/cathode electrically connected to a second terminal. The integrated circuit device additionally includes a plurality of metallization levels formed above the semiconductor substrate. The integrated circuit device further includes a triggering device formed in the semiconductor substrate on a first side and adjacent to the bidirectional SCR. The triggering device includes one or more of a bipolar junction transistor (BJT) or an avalanche PN diode, where a first device terminal of the triggering device is commonly connected to the T1 with the K/A, and where a second device terminal of the triggering device is electrically connected to a central region of the bidirectional SCR through one or more of the metallization levels.
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