公开(公告)号：US20240206172A1

公开(公告)日：2024-06-20

申请号：US18425633

申请日：2024-01-29

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Mihaela A. Balseanu

IPC分类号： H10B43/27 ,  H01L21/28 ,  H01L21/67 ,  H01L21/687 ,  H01L29/423

CPC分类号： H10B43/27 ,  H01L21/67167 ,  H01L21/68707 ,  H01L29/40117 ,  H01L29/4234

摘要： Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

公开(公告)号：US11594537B2

公开(公告)日：2023-02-28

申请号：US17354254

申请日：2021-06-22

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima

IPC分类号： H01L27/108

摘要： Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.

公开(公告)号：US11587930B2

公开(公告)日：2023-02-21

申请号：US17159534

申请日：2021-01-27

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Nitin K. Ingle ,  Sung-Kwan Kang

IPC分类号： H01L27/108 ,  H01L27/12 ,  H01L29/66 ,  H01L29/423 ,  H01L29/786

摘要： Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.

公开(公告)号：US20230040627A1

公开(公告)日：2023-02-09

申请号：US17879097

申请日：2022-08-02

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sung-Kwan Kang

IPC分类号： H01L27/11524 ,  G11C16/04 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

摘要： Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.

公开(公告)号：US20210399011A1

公开(公告)日：2021-12-23

申请号：US17346910

申请日：2021-06-14

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Mihaela A. Balseanu

IPC分类号： H01L27/11582 ,  H01L29/423 ,  H01L21/28 ,  H01L21/67 ,  H01L21/687

摘要： Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.

公开(公告)号：US11189635B2

公开(公告)日：2021-11-30

申请号：US16833899

申请日：2020-03-30

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Mukund Srinivasan ,  Sanjay Natarajan

IPC分类号： H01L27/11582 ,  H01L29/792 ,  H01L27/11575 ,  H01L21/3205 ,  H01L21/311 ,  H01L21/677 ,  H01L21/02 ,  H01L21/3213

摘要： Methods of manufacturing memory devices are provided. The methods decrease the thickness of the first layers and increase the thickness of the second layers. Semiconductor devices are described having a film stack comprising alternating nitride and second layers in a first portion of the device, the alternating nitride and second layers of the film stack having a nitride:oxide thickness ratio (Nf:Of); and a memory stack comprising alternating word line and second layers in a second portion of the device, the alternating word line and second layers of the memory stack having a word line:oxide thickness ratio (Wm:Om), wherein 0.1(Wm:Om)

公开(公告)号：US11158650B2

公开(公告)日：2021-10-26

申请号：US16657583

申请日：2019-10-18

申请人： Applied Materials, Inc.

发明人： ChangSeok Kang ,  Tomohiko Kitajima

IPC分类号： H01L23/48 ,  H01L27/11582 ,  H01L23/532 ,  H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/67

摘要： Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.

公开(公告)号：US20210233779A1

公开(公告)日：2021-07-29

申请号：US17147578

申请日：2021-01-13

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Sung-Kwan Kang

IPC分类号： H01L21/321 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11582

摘要： Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.

公开(公告)号：US20200251151A1

公开(公告)日：2020-08-06

申请号：US16779830

申请日：2020-02-03

申请人： Applied Materials, Inc.

发明人： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC分类号： G11C5/06 ,  H01L27/108

摘要： Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US20160018815A1

公开(公告)日：2016-01-21

申请号：US14333395

申请日：2014-07-16

申请人： Applied Materials, Inc.

发明人： Tomohiko Kitajima ,  Jeffrey Drue David ,  Jun Qian ,  Taketo Sekine ,  Garlen C. Leung ,  Sidney P. Huey

IPC分类号： G05B19/418

CPC分类号： G05B19/418 ,  B24B37/013 ,  G05B2219/45031 ,  G05B2219/45232 ,  G05B2219/49085 ,  H01L21/31053 ,  H01L22/12 ,  H01L22/26 ,  Y02P90/02

摘要： A method of controlling polishing includes storing a base spectrum, the base spectrum being a spectrum of light reflected from a substrate after deposition of a deposited dielectric layers overlying a metallic layer or semiconductor wafer and before deposition of a non-metallic layer over the plurality of deposited dielectric layer. After deposition of the non-metallic layer and during polishing of the non-metallic layer on the substrate, measurements of a sequence of raw spectra of light reflected the substrate during polishing are received from an in-situ optical monitoring system. Each raw spectrum is normalized to generate a sequence of normalized spectra using the raw spectrum and the base spectrum. At least one of a polishing endpoint or an adjustment for a polishing rate is determined based on at least one normalized predetermined spectrum from the sequence of normalized spectra.

摘要翻译： 控制抛光的方法包括：存储基色谱，所述基色谱是在沉积覆盖在金属层或半导体晶片上的沉积的介电层之后并且在非金属层上沉积多个 沉积介电层。 在沉积非金属层之后并且在非金属层的抛光过程中，从原位光学监测系统接收在抛光期间反射基板的原始光谱序列的测量。 对每个原始光谱进行归一化，以使用原始光谱和基色谱产生归一化光谱序列。 基于归一化光谱序列中的至少一个归一化的预定光谱来确定抛光终点或抛光速率的调整中的至少一个。