公开(公告)号：US11626410B2

公开(公告)日：2023-04-11

申请号：US17861412

申请日：2022-07-11

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US20200235104A1

公开(公告)日：2020-07-23

申请号：US16839392

申请日：2020-04-03

Applicant: Applied Materials, Inc.

Inventor： Priyadarshi Panda ,  Jianxin Lei ,  Wenting Hou ,  Mihaela Balseanu ,  Ning Li ,  Sanjay Natarajan ,  Gill Yong Lee ,  In Seok Hwang ,  Nobuyuki Sasaki ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L21/3213 ,  H01L21/033

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

公开(公告)号：US20190088540A1

公开(公告)日：2019-03-21

申请号：US15711169

申请日：2017-09-21

Applicant: APPLIED MATERIALS, INC.

Inventor： Wenting Hou ,  Jianxin Lei ,  Joung Joo Lee ,  Rong Tao

IPC: H01L21/768 ,  C23C16/06 ,  C23C14/14

Abstract: Methods and apparatus for filling features with cobalt are provided herein. In some embodiments, a method for processing a substrate includes: depositing a first cobalt layer via a chemical vapor deposition (CVD) process atop a substrate and within a feature disposed in the substrate; and at least partially filling the feature with cobalt or cobalt containing material by performing a plasma process in a physical vapor deposition (PVD) chamber having a cobalt target to reflow a portion of the first cobalt layer into the feature. The PVD chamber may be configured to simultaneously deposit cobalt or cobalt containing material within the feature from a cobalt target disposed in the PVD chamber.

公开(公告)号：US20240175120A1

公开(公告)日：2024-05-30

申请号：US18512894

申请日：2023-11-17

Applicant: Applied Materials, Inc.

Inventor： Tsung-Han Yang ,  Zhen Liu ,  Yongqian Gao ,  Wenting Hou ,  Rongjun Wang

IPC: C23C16/04 ,  C23C16/06 ,  H01L21/768 ,  H01L23/532

CPC classification number: C23C16/045 ,  C23C16/06 ,  H01L21/76843 ,  H01L21/76876 ,  H01L21/76877 ,  H01L23/53266

Abstract: Embodiments of the disclosure relate to methods for metal gapfill with lower resistivity. Specific embodiments provide methods of forming a tungsten gapfill without a high resistance nucleation layer. Some embodiments of the disclosure utilize a nucleation underlayer to promote growth of the metal gapfill.

公开(公告)号：US11637107B2

公开(公告)日：2023-04-25

申请号：US17351223

申请日：2021-06-17

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US20220406788A1

公开(公告)日：2022-12-22

申请号：US17351223

申请日：2021-06-17

Applicant: Applied Materials, Inc.

Inventor： Tom Ho Wing Yu ,  Nobuyuki Sasaki ,  Jianxin Lei ,  Wenting Hou ,  Rongjun Wang ,  Tza-Jing Gung

IPC: H01L27/108

Abstract: Bit line stacks and methods of forming bit line stacks are described herein. A bit line stack comprises: a polysilicon layer; an adhesion layer on the polysilicon layer; a barrier metal layer on the adhesion layer; an interface layer on the barrier metal layer; a resistance reducing layer on the interface layer; and a conductive layer on the resistance reducing layer. A bit line stack having the resistance reducing layer has a resistance at least 5% lower than a comparable bit line stack without the resistance reducing layer. The resistance reducing layer may include silicon oxide or silicon nitride. The resistance reducing layer may be formed using one or more of a physical vapor deposition (PVD), a radio frequency-PVD, a pulsed-PVD, chemical vapor deposition (CVD), atomic layer deposition (ALD) or sputtering process.

公开(公告)号：US20220231137A1

公开(公告)日：2022-07-21

申请号：US17152190

申请日：2021-01-19

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Joung Joo Lee ,  Wenting Hou ,  Takashi Kuratomi ,  Avgerinos V. Gelatos ,  Jianxin Lei ,  Liqi Wu ,  Raymond Hoiman Hung ,  Tae Hong Ha ,  Xianmin Tang

IPC: H01L29/417 ,  H01L21/285 ,  H01L21/8234

Abstract: A contact stack of a semiconductor device comprises: a source/drain region; a metal silicide layer above the source/drain region; a metal cap layer directly on the metal silicide layer; and a conductor on the metal cap layer. A method comprises: depositing a metal silicide layer in a feature of a substrate; in the absence of an air break after the depositing of the metal silicide layer, preparing a metal cap layer directly on the metal silicide layer; and depositing a conductor on the metal cap layer.

公开(公告)号：US11908696B2

公开(公告)日：2024-02-20

申请号：US17569870

申请日：2022-01-06

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Mehul Naik ,  Wenting Hou ,  Jianxin Lei ,  Chen Gong ,  Yong Cao

IPC: H01L21/285 ,  H01L21/768 ,  C23C14/56 ,  C23C14/14 ,  C23C14/24 ,  C23C14/06

CPC classification number: H01L21/2855 ,  C23C14/0641 ,  C23C14/14 ,  C23C14/24 ,  C23C14/56 ,  H01L21/76829 ,  H01L21/76876

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.

公开(公告)号：US10950500B2

公开(公告)日：2021-03-16

申请号：US15971573

申请日：2018-05-04

Applicant: APPLIED MATERIALS, INC.

Inventor： Roey Shaviv ,  Xikun Wang ,  Ismail Emesh ,  Jianxin Lei ,  Wenting Hou

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/02 ,  H01L23/532

Abstract: Embodiments of methods and apparatus for filling a feature disposed in a substrate are disclosed herein. In some embodiments, a method for filling a feature disposed in a substrate includes (a) depositing a metal within the feature to a first predetermined thickness in a first process chamber; (b) depositing the metal within the feature to a second predetermined thickness in a second process chamber; (c) etching the metal deposited in (b) to remove an overhang of the metal at a top of the feature in a third process chamber different than the first and second process chambers; and (d) subsequent to (c), filling the feature with the metal in a fourth process chamber different than the first and third process chambers.

公开(公告)号：US10304732B2

公开(公告)日：2019-05-28

申请号：US15711169

申请日：2017-09-21

Applicant: APPLIED MATERIALS, INC.

Inventor： Wenting Hou ,  Jianxin Lei ,  Joung Joo Lee ,  Rong Tao

IPC: H01L21/768 ,  H01L21/67 ,  C23C14/14 ,  C23C16/06 ,  H01L21/285 ,  H01L21/02 ,  H01L23/532

Abstract: Methods and apparatus for filling features with cobalt are provided herein. In some embodiments, a method for processing a substrate includes: depositing a first cobalt layer via a chemical vapor deposition (CVD) process atop a substrate and within a feature disposed in the substrate; and at least partially filling the feature with cobalt or cobalt containing material by performing a plasma process in a physical vapor deposition (PVD) chamber having a cobalt target to reflow a portion of the first cobalt layer into the feature. The PVD chamber may be configured to simultaneously deposit cobalt or cobalt containing material within the feature from a cobalt target disposed in the PVD chamber.