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公开(公告)号：US20240329153A1
公开(公告)日：2024-10-03
申请号：US18127871
申请日：2023-03-29
Applicant: Arm Limited
Inventor： Ashwani Kumar Srivastava , Yves Thomas Laplanche , Ramesh Manohar
IPC: G01R31/52
CPC classification number: G01R31/52
Abstract: Various implementations described herein are related to a device with fabrication test circuitry having transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In some applications, each transistor in an off-current branch may be separately deactivated so as to test leakage current applied to the pad by way of the off-current branch, and also, each transistor in an on-current branch may be deactivated so as to further test the leakage current applied to the pad by way of the off-current branch.
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公开(公告)号：US20230063727A1
公开(公告)日：2023-03-02
申请号：US17462524
申请日：2021-08-31
Applicant: Arm Limited
Inventor： Anil Kumar Baratam , Yves Thomas Laplanche
IPC: H03K19/007 , H03K19/173 , H03K19/096
Abstract: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.
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公开(公告)号：US11315927B2
公开(公告)日：2022-04-26
申请号：US16387440
申请日：2019-04-17
Applicant: Arm Limited
Inventor： Sreejith Mohan , Buchupalli Venkata Chaitanya Reddy , Abhilash Velluridathil Thazhathidathil , Yves Thomas Laplanche
IPC: H01L27/092 , H01L29/06
Abstract: Various implementations described herein are directed to device having a regular well cell and a flipped well cell. The regular well cell has a first N-well and a first P-well, and the flipped well cell has a second N-well and a second P-well in complementary relationship with the first N-well and the first P-well of the regular well cell. The device includes a bridge cell disposed between the regular well cell and the flipped well cell.
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公开(公告)号：US20200335502A1
公开(公告)日：2020-10-22
申请号：US16387440
申请日：2019-04-17
Applicant: Arm Limited
Inventor： Sreejith Mohan , Buchupalli Venkata Chaitanya Reddy , Abhilash Velluridathil Thazhathidathil , Yves Thomas Laplanche
IPC: H01L27/092 , H01L29/06
Abstract: Various implementations described herein are directed to device having a regular well cell and a flipped well cell. The regular well cell has a first N-well and a first P-well, and the flipped well cell has a second N-well and a second P-well in complementary relationship with the first N-well and the first P-well of the regular well cell. The device includes a bridge cell disposed between the regular well cell and the flipped well cell.
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公开(公告)号：US12068745B2
公开(公告)日：2024-08-20
申请号：US17462524
申请日：2021-08-31
Applicant: Arm Limited
Inventor： Anil Kumar Baratam , Yves Thomas Laplanche
IPC: H03K19/007 , H03K19/096 , H03K19/173
CPC classification number: H03K19/0075 , H03K19/096 , H03K19/1737
Abstract: Various implementations described herein are directed to a device having a scan chain that receives a multi-bit input, provides a multi-bit output, and provides a multi-bit multiplexer output based on the multi-bit input and the multi-bit output. The device may have an error-bit generator that receives the multi-bit multiplexer output, receives a portion of the multi-bit input, receives a portion of the multi-bit output, and provides an error-bit output based on the multi-bit multiplexer output, the portion of the multi-bit input, and the portion of the multi-bit output.
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Patent Agency Ranking
公开(公告)号：US20240249790A1
公开(公告)日：2024-07-25
申请号：US18100614
申请日：2023-01-24
Applicant: Arm Limited
Inventor： Yannis Jallamion-Grive , Yunpeng Cai , Mohammed Adnan Addou , Anil Kumar Baratam , Denil Das Kolady , Chandru Tavarekere Krishnegowda , Jad Mohdad , Yves Thomas Laplanche , Yannick Marc Nevers
CPC classification number: G11C29/30 , G11C29/1201 , G11C29/12015 , G11C2029/3202
Abstract: Various implementations described herein are related to a device having a memory architecture with a register bank and multiple latches. The multiple latches may have first latches that receive multi-bit data as input and provide the multi-bit data as output, and multiple latches may have second latches coupled to the first latches so as to receive the multi-bit data from the first latches and then store the multi-bit data.
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公开(公告)号：US10355674B2
公开(公告)日：2019-07-16
申请号：US15658214
申请日：2017-07-24
Applicant: ARM Limited
Inventor： Anil Kumar Baratam , Nruthya Nagesh Prabhu , Yves Thomas Laplanche
IPC: H03K3/356 , H03K17/687
Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.
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公开(公告)号：US11900041B2
公开(公告)日：2024-02-13
申请号：US16653778
申请日：2019-10-15
Applicant: Arm Limited
IPC: G06F30/398 , G06F30/30 , G06F30/392
CPC classification number: G06F30/398 , G06F30/30 , G06F30/392
Abstract: In a particular implementation, a method includes: identifying prospective zones for placement of one or more vertical interconnect access pads (via) in a cell, where each of the prospective zones comprises one or more poly pitches; and assigning a first color for a particular poly pitch of a first identified zone of the identified prospective zones or assigning a first color sequence for one or more sections of the first identified zone.
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公开(公告)号：US20210109999A1
公开(公告)日：2021-04-15
申请号：US16653778
申请日：2019-10-15
Applicant: Arm Limited
IPC: G06F17/50
Abstract: In a particular implementation, a method includes: identifying prospective zones for placement of one or more vertical interconnect access pads (via) in a cell, where each of the prospective zones comprises one or more poly pitches; and assigning a first color for a particular poly pitch of a first identified zone of the identified prospective zones or assigning a first color sequence for one or more sections of the first identified zone.
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公开(公告)号：US20190028091A1
公开(公告)日：2019-01-24
申请号：US15658214
申请日：2017-07-24
Applicant: ARM Limited
Inventor： Anil Kumar Baratam , Nruthya Nagesh Prabhu , Yves Thomas Laplanche
IPC: H03K3/356 , H03K17/687
CPC classification number: H03K3/356121 , H03K3/012 , H03K17/6872
Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.
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