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公开(公告)号：US20140331069A1
公开(公告)日：2014-11-06
申请号：US13875199
申请日：2013-05-01
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Alexander Branover , Steven Kommrusch , Marvin Denman , Maurice Steinman
IPC: G06F1/28
CPC classification number: G06F1/206 , G06F1/26 , G06F1/3234 , Y02D10/16
Abstract: An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed.
Abstract translation: 接口将多个计算单元耦合到电力管理控制器。 该接口将多个计算单元的功率报告传送给电力管理控制器。 功率管理控制器接收功率报告，至少部分基于功率报告确定多个计算单元的功率动作，并通过接口发送指定功率动作的消息。 执行动作动作。
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公开(公告)号：US08832485B2
公开(公告)日：2014-09-09
申请号：US13854616
申请日：2013-04-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
CPC classification number: G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
Abstract translation: 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。
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公开(公告)号：US20190033939A1
公开(公告)日：2019-01-31
申请号：US15663464
申请日：2017-07-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Sonu Arora , Alexander Branover , Benjamin Tsien
CPC classification number: G06F1/266 , G06F1/189 , G06F1/26 , G06F13/1673
Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.
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Patent Agency Ranking
公开(公告)号：US10474211B2
公开(公告)日：2019-11-12
申请号：US15663464
申请日：2017-07-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Sonu Arora , Alexander Branover , Benjamin Tsien
Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.
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公开(公告)号：US20130283078A1
公开(公告)日：2013-10-24
申请号：US13919306
申请日：2013-06-17
Applicant: Advanced Micro Devices, Inc
Inventor： Alexander Branover , Maurice B. Steinman , William L. Bircher
IPC: G06F1/32
CPC classification number: G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
Abstract translation: 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。
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公开(公告)号：US20130227321A1
公开(公告)日：2013-08-29
申请号：US13854616
申请日：2013-04-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Norman M. Hack , Maurice B. Steinman , John Kalamatianos , Jonathan M. Owen
IPC: G06F1/32
CPC classification number: G06F1/3275 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F12/0864 , G06F2212/1028 , Y02D10/126 , Y02D10/13 , Y02D10/14 , Y02D10/172
Abstract: A method and apparatus for dynamically controlling a cache size is disclosed. In one embodiment, a method includes changing an operating point of a processor from a first operating point to a second operating point, and selectively removing power from one or more ways of a cache memory responsive to changing the operating point. The method further includes processing one or more instructions in the processor subsequent to removing power from the one or more ways of the cache memory, wherein said processing includes accessing one or more ways of the cache memory from which power was not removed.
Abstract translation: 公开了一种用于动态控制高速缓存大小的方法和装置。 在一个实施例中，一种方法包括将处理器的操作点从第一操作点改变到第二操作点，以及响应于改变操作点而选择性地从高速缓冲存储器的一种或多种方式去除功率。 该方法还包括在从高速缓冲存储器的一个或多个方式移除电力之后处理处理器中的一个或多个指令，其中所述处理包括访问未去除功率的高速缓冲存储器的一种或多种方式。
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公开(公告)号：US09360906B2
公开(公告)日：2016-06-07
申请号：US13875199
申请日：2013-05-01
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Steven Kommrusch , Marvin Denman , Maurice Steinman
CPC classification number: G06F1/206 , G06F1/26 , G06F1/3234 , Y02D10/16
Abstract: An interface couples a plurality of compute units to a power management controller. The interface conveys a power report for the plurality of compute units to the power management controller. The power management controller receives the power report, determines a power action for the plurality of compute units based at least in part on the power report, and transmits a message specifying the power action through the interface. The power action is performed.
Abstract translation: 接口将多个计算单元耦合到电力管理控制器。 该接口将多个计算单元的功率报告传送给电力管理控制器。 功率管理控制器接收功率报告，至少部分基于功率报告确定多个计算单元的功率动作，并通过接口发送指定功率动作的消息。 执行动作动作。
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公开(公告)号：US08959372B2
公开(公告)日：2015-02-17
申请号：US13919306
申请日：2013-06-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Alexander Branover , Maurice B Steinman , William L Bircher
CPC classification number: G06F1/3215 , G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.
Abstract translation: 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。
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