公开(公告)号：US20150198991A1

公开(公告)日：2015-07-16

申请号：US14152826

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Bircher ,  Madhu Saravana Sibi Govindan ,  Manish Arora ,  Michael J. Schulte ,  Nuwan S. Jayasena

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

Abstract translation: 电源管理状态的持续时间是以每个进程为基础预测的。 一些实施例包括在与一个或多个进程相关联的一个或多个数据结构中存储指示与进程相关联的电力管理状态的先前持续时间的信息。 一些实施例还包括使用存储在数据结构中的信息来预测过程的功率管理状态的后续持续时间。

公开(公告)号：US20130283078A1

公开(公告)日：2013-10-24

申请号：US13919306

申请日：2013-06-17

Applicant: Advanced Micro Devices, Inc

Inventor： Alexander Branover ,  Maurice B. Steinman ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3215 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: An apparatus and method for performance control of processing nodes is disclosed. In one embodiment, a system includes a processing node and a power management unit configured to, for each of a plurality of time intervals, monitor an activity level of the processing node, cause the processing node to operate at a high operating point during one successive time interval if the activity level in the given interval is greater than a high activity threshold, operate at a low operating point at least one successive time interval if the activity level is less than a low activity threshold, or enable operating system software to cause the processing node to operate at one of one or more predefined intermediate operating points of the plurality of operating points if the activity level is less than the high activity threshold and greater than the low activity threshold.

Abstract translation: 公开了一种用于处理节点的性能控制的装置和方法。 在一个实施例中，系统包括处理节点和功率管理单元，其被配置为针对多个时间间隔中的每一个监视处理节点的活动级别，使处理节点在连续的连续操作期间在高操作点 时间间隔，如果给定间隔中的活动水平大于高活动阈值，则如果活动水平低于低活动阈值，则在低操作点操作至少一个连续时间间隔，或使得操作系统软件能够使 处理节点在多个操作点的一个或多个预定义的中间操作点之一操作，如果活动水平小于高活动阈值并且大于低活动阈值。

公开(公告)号：US20160342354A1

公开(公告)日：2016-11-24

申请号：US14716314

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Madhu S. S. Govindan ,  William L. Bircher

IPC: G06F3/06

CPC classification number: G06F1/32 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172

Abstract: A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector.The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.

Abstract translation: 在修改给定扇区后，给定扇区的需要冲洗标志被置位，并在保存状态操作后清零。

公开(公告)号：US20140173298A1

公开(公告)日：2014-06-19

申请号：US13717992

申请日：2012-12-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Bircher ,  Madhu Saravana Sibi Govindan ,  Brian E. Waldecker

IPC: G06F1/26

CPC classification number: G06F1/3203

Abstract: Methods, systems, and media are provided for power management. The power management includes, but is not limited to storing at a computer system a history of canceled entries into a low power state that interrupted a transition of the unit from an active mode to the low power state and disallowing transition of the unit into the low power state when a number of canceled entries indicated by the history of canceled entries exceeds a canceled entry threshold.

Abstract translation: 提供方法，系统和媒体用于电源管理。 电源管理包括但不限于在计算机系统中将取消的条目的历史记录到中断从单位从活动模式转换到低功率状态的低功率状态，并且禁止将单元转换到低电平状态 当由取消的条目的历史指示的许多取消的条目超过取消的入口阈值时，电源状态。

公开(公告)号：US09946319B2

公开(公告)日：2018-04-17

申请号：US14059384

申请日：2013-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Manish Arora ,  Srilatha Manne ,  William L. Bircher

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3206 ,  G06F1/206

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

公开(公告)号：US09720487B2

公开(公告)日：2017-08-01

申请号：US14152826

申请日：2014-01-10

Applicant: Advanced Micro Devices, Inc.

Inventor： William L. Bircher ,  Madhu Saravana Sibi Govindan ,  Manish Arora ,  Michael J. Schulte ,  Nuwan S. Jayasena

IPC: G06F1/32

CPC classification number: G06F1/3243 ,  G06F1/3287 ,  G06F1/329 ,  Y02D10/152 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D50/20

Abstract: Durations of power management states are predicted on a per-process basis. Some embodiments include storing, in one or more data structures associated with one or more processes, information indicating previous durations of a power management state associated with the process(es). Some embodiments also include predicting a subsequent duration of the power management state for the process(es) using information stored in the data structure(s).

公开(公告)号：US09851777B2

公开(公告)日：2017-12-26

申请号：US14146591

申请日：2014-01-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Indrani Paul ,  Yasuko Eckert ,  Nuwan S. Jayasena ,  Srilatha Manne ,  Madhu Saravana Sibi Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3225 ,  Y02D10/171 ,  Y02D50/20

Abstract: Power gating decisions can be made based on measures of cache dirtiness. Analyzer logic can selectively power gate a component of a processor system based on a cache dirtiness of one or more caches associated with the component. The analyzer logic may power gate the component when the cache dirtiness exceeds a threshold and may maintains the component in an idle state when the cache dirtiness does not exceed the threshold. Idle time prediction logic may be used to predict a duration of an idle time of the component. The analyzer logic may then selectively power gates the component based on the cache dirtiness and the predicted idle time.

公开(公告)号：US09760145B2

公开(公告)日：2017-09-12

申请号：US14716314

申请日：2015-05-19

Applicant: Advanced Micro Devices, Inc.

Inventor： Madhu S. S. Govindan ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/32 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/172

Abstract: A system for saving the architectural state of a processor is described. The system performs a save state operation, which involves, for each sector in a set of sectors of the architectural state, determining whether the architectural state for the sector has already been saved to a memory, and saving the architectural state for the sector to the memory when the architectural state for the sector has not already been saved to the memory. Each sector in the set of sectors comprises a different and separate portion of the architectural state of the processor. The system determines whether the architectural state for a given sector has already been saved to the memory by checking a needs-rinsing flag for the given sector. The needs-rinsing flag for the given sector is asserted upon modifying the given sector and cleared following the save state operation.

公开(公告)号：US20140143565A1

公开(公告)日：2014-05-22

申请号：US14059384

申请日：2013-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Indrani Paul ,  Manish Arora ,  Srilatha Manne ,  William L. Bircher

IPC: G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/206

Abstract: The described embodiments include a computing device with a first entity and a second entity. In the computing device, a management controller dynamically sets a power-state limit for the first entity based on a performance coupling and a thermal coupling between the first entity and the second entity.

Abstract translation: 所描述的实施例包括具有第一实体和第二实体的计算设备。 在计算设备中，管理控制器基于第一实体和第二实体之间的性能耦合和热耦合来动态地设置第一实体的功率状态极限。

公开(公告)号：US09442557B2

公开(公告)日：2016-09-13

申请号：US14075645

申请日：2013-11-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Manish Arora ,  Nuwan S. Jayasena ,  Yasuko Eckert ,  Madhu Saravana Sibi Govindan ,  William L. Bircher ,  Michael J. Schulte ,  Srilatha Manne

IPC: G06F1/32 ,  G06F1/20

CPC classification number: G06F1/3234 ,  G06F1/206

Abstract: The described embodiments include a computing device with one or more entities (processor cores, processors, etc.). In some embodiments, during operation, a thermal power management unit in the computing device uses a linear prediction to compute a predicted duration of a next idle period for an entity based on the duration of one or more previous idle periods for the entity. Based on the predicted duration of the next idle period, the thermal power management unit configures the entity to operate in a corresponding idle state.

Abstract translation: 所描述的实施例包括具有一个或多个实体（处理器核心，处理器等）的计算设备。 在一些实施例中，在操作期间，计算设备中的热功率管理单元使用线性预测来基于实体的一个或多个先前空闲周期的持续时间来计算实体的下一个空闲周期的预测持续时间。 基于下一个空闲周期的预测持续时间，热功率管理单元将实体配置为在相应的空闲状态下工作。