公开(公告)号：US09159409B2

公开(公告)日：2015-10-13

申请号：US13623937

申请日：2012-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Donald R. Weiss

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0061 ,  G11C14/0081 ,  G11C14/009 ,  G11C2213/77

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract translation: 一种方法，集成电路和装置可操作以控制多个可变电阻存储器单元以从至少一个有效存储器电路（诸如触发器，锁存器或任何其它合适的状态产生电路）存储互补状态信息。 该方法，装置和集成电路可操作以控制多个可变电阻存储器单元，以还恢复存储的至少一个有效存储器的互补状态信息。

公开(公告)号：US09575891B2

公开(公告)日：2017-02-21

申请号：US14307164

申请日：2014-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC: G06F12/00 ,  G06F12/06 ,  G11C5/02

CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。

公开(公告)号：US20150364168A1

公开(公告)日：2015-12-17

申请号：US14307164

申请日：2014-06-17

Applicant: Advanced Micro Devices, Inc.

Inventor： John R. Riley ,  Russell Schreiber ,  Donald R. Weiss ,  John J. Wuu ,  William A. McGee

IPC: G11C7/18 ,  G11C11/406 ,  G06F12/06

CPC classification number: G06F12/0607 ,  G06F12/0623 ,  G06F2212/1052 ,  G06F2212/2532 ,  G11C5/025

Abstract: A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. The memory includes at least a primary bank and a sidecar bank. The primary bank includes a first portion with (M−A) bits of the M bits of a memory line being accessed. The sidecar bank includes a second portion with A bits of the M bits of the memory line being accessed. The primary bank and the sidecar bank have a same height, which is less than a height that would be used if the primary bank included all M bits in each memory line. The completion of the access request for the M bits of the memory line is done at a similar time, such as a same clock cycle.

Abstract translation: 用于布局规划存储器的系统和方法。 计算系统包括生成存储器访问请求的处理单元和存储器。 存储器中每个存储器线的大小包括M位。 记忆体至少包括一个主要银行和一个侧边银行。 主存储体包括第一部分，存取存储器线的M位的（M-A）位。 旁边组包括存取线的M位的A位的第二部分。 主要银行和旁边银行的高度相同，如果主存储包含每个存储行中的所有M位，则低于要使用的高度。 对于存储器线路的M位的访问请求的完成在类似的时间完成，例如相同的时钟周期。

公开(公告)号：US20130069964A1

公开(公告)日：2013-03-21

申请号：US13623937

申请日：2012-09-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John J. Wuu ,  Donald R. Weiss

IPC: G06T1/60 ,  H01L21/8239 ,  G11C11/34

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0061 ,  G11C14/0081 ,  G11C14/009 ,  G11C2213/77

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract translation: 一种方法，集成电路和装置可操作以控制多个可变电阻存储器单元以从至少一个有效存储器电路（诸如触发器，锁存器或任何其它合适的状态产生电路）存储互补状态信息。 该方法，装置和集成电路可操作以控制多个可变电阻存储器单元，以还恢复存储的至少一个有效存储器的互补状态信息。

公开(公告)号：US20130083048A1

公开(公告)日：2013-04-04

申请号：US13629675

申请日：2012-09-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald R. Weiss

IPC: G11C11/34 ,  G06T1/60 ,  H01L45/00

CPC classification number: G11C16/0408 ,  G11C11/16 ,  G11C13/0002 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0023 ,  G11C16/08 ,  G11C2213/71 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

Abstract: An integrated circuit includes, in one example, an active memory cell array and a passive variable resistance memory cell array positioned above the active memory cell array, such as in upper layers of the integrated circuit. The active memory cell array and the passive variable resistance memory cell array share one or more components of memory control logic such as address decode logic, data read logic and/or data write logic. As such, a type of active memory and passive variable resistance memory hybrid structure shares memory control logic such as word line drivers, bit line drivers and read logic. The active memory cell array and passive variable resistance memory cell array overlap reducing integrated circuit die size, improving power reduction and reducing costs by sharing peripheral circuits.

Abstract translation: 在一个示例中，集成电路包括位于有源存储器单元阵列上方的有源存储单元阵列和可变电阻存储单元阵列，例如在集成电路的上层中。 有源存储单元阵列和无源可变电阻存储单元阵列共享存储器控制逻辑的一个或多个组件，例如地址解码逻辑，数据读取逻辑和/或数据写入逻辑。 因此，一种有源存储器和可变可变电阻存储器混合结构共享存储器控制逻辑，例如字线驱动器，位线驱动器和读逻辑。 有源存储单元阵列和无源可变电阻存储单元阵列重叠减少集成电路管芯尺寸，通过共享外围电路来提高功耗并降低成本。