公开(公告)号：US5699297A

公开(公告)日：1997-12-16

申请号：US654886

申请日：1996-05-29

申请人： Akihiro Yamazaki ,  Takamichi Kasai

发明人： Akihiro Yamazaki ,  Takamichi Kasai

IPC分类号： G11C16/10 ,  G11C16/34 ,  G11C11/34

CPC分类号： G11C16/3431 ,  G11C16/102 ,  G11C16/105 ,  G11C16/3418

摘要： The present invention relates to a method of rewriting data in a microcomputer additionally provided with a flash memory having a refresh mode, in which the data retained in an area arbitrarily specified in the flash memory is transferred to a RAM for temporary evacuation and after the data in the area has been erased, the data evacuated to the flash memory is written into the area again.

摘要翻译： 本发明涉及一种在微计算机中重新写入数据的方法，该微计算机还具备具有刷新模式的闪速存储器，其中保留在闪速存储器中任意指定的区域中的数据被传送到用于临时撤离的RAM和数据 在该区域已经被擦除的情况下，将撤离到闪速存储器的数据再次写入该区域。

公开(公告)号：US07573765B2

公开(公告)日：2009-08-11

申请号：US11846026

申请日：2007-08-28

申请人： Hideyoshi Takai ,  Takamichi Kasai

发明人： Hideyoshi Takai ,  Takamichi Kasai

IPC分类号： G11C7/00

CPC分类号： G11C8/10 ,  G11C29/02 ,  G11C29/024 ,  G11C29/18 ,  G11C2029/3602

摘要： A semiconductor memory device 100 is proposed including an internal address generation circuit 3, a first internal address control signal generation part 4, a second internal address control signal generation part 11, and an internal address control signal selection circuit 10 having an OR gate transistor 12. The internal address generation circuit 3 generates an internal address signal based on input address data. The first internal address control signal generation part 4 generates a first internal address control signal and having a function which fixes the first internal address control signal at a predetermined level with the elapse of a fixed period of time. The second internal address control signal generation part 11 generates a second internal address control signal corresponding to an input of a predetermined command. The OR gate transistor 12 transmits either the first internal address control signal or the second internal address control signal to the internal address generation circuit 3.

摘要翻译： 提出了一种半导体存储器件100，其包括内部地址产生电路3，第一内部地址控制信号产生部分4，第二内部地址控制信号产生部分11和具有或门晶体管12的内部地址控制信号选择电路10 内部地址生成电路3基于输入地址数据生成内部地址信号。 第一内部地址控制信号产生部分4产生第一内部地址控制信号，并且具有在经过一段固定时间段时将第一内部地址控制信号固定在预定电平的功能。 第二内部地址控制信号产生部分11产生与预定命令的输入相对应的第二内部地址控制信号。 或门晶体管12将第一内部地址控制信号或第二内部地址控制信号发送到内部地址产生电路3。

公开(公告)号：US20120243328A1

公开(公告)日：2012-09-27

申请号：US13229938

申请日：2011-09-12

申请人： Keiji Tatebe ,  Takamichi Kasai

发明人： Keiji Tatebe ,  Takamichi Kasai

IPC分类号： G11C16/14

CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/345

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell array includes a plurality of pages formed in a common semiconductor region, each of the pages includes a plurality of electrically programmable memory cells, a control circuit configured to performs an erase operation for a selected page, and a verification circuit configured to verify a threshold value of the memory cell array after the erase operation. The verification circuit uses a first erase verification voltage when verifying the selected page, and a second erase verification voltage different from the first erase verification voltage when verifying an unselected page.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括存储单元阵列，其包括形成在公共半导体区域中的多个页面，每个页面包括多个电可编程存储器单元，控制电路被配置为执行擦除操作 选择页面，以及配置为在擦除操作之后验证存储单元阵列的阈值的验证电路。 当验证所选择的页面时，验证电路使用第一擦除验证电压，并且在验证未选择的页面时使用与第一擦除验证电压不同的第二擦除验证电压。

公开(公告)号：US20120243319A1

公开(公告)日：2012-09-27

申请号：US13229949

申请日：2011-09-12

申请人： Takamichi Kasai ,  Tomonori Noguchi

发明人： Takamichi Kasai ,  Tomonori Noguchi

IPC分类号： G11C16/30

CPC分类号： G11C16/30 ,  G11C16/0416 ,  G11C16/10

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes a first nonvolatile memory, and a voltage generation circuit configured to apply a voltage to the first nonvolatile memory, the voltage generation circuit includes a charge pump and an oscillator configured to generate a clock to be used to operate the charge pump. The voltage generation circuit changes a frequency of the clock.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一非易失性存储器和被配置为向第一非易失性存储器施加电压的电压产生电路，电压产生电路包括电荷泵和振荡器，其被配置为产生时钟 用于操作电荷泵。 电压产生电路改变时钟的频率。

公开(公告)号：US20060227621A1

公开(公告)日：2006-10-12

申请号：US11401418

申请日：2006-04-11

申请人： Takamichi Kasai ,  Hideo Kato

发明人： Takamichi Kasai ,  Hideo Kato

IPC分类号： G11C16/04

CPC分类号： G11C29/838 ,  G11C16/04 ,  G11C29/52 ,  G11C29/76

摘要： A nonvolatile semiconductor memory includes a cell array, redundancy array, erase circuit, timer, and controller. The cell array has a plurality of memory cells. The redundancy array has a plurality of redundant cells capable of replacing the memory cell. The erase circuit performs an erase operation on a target cell including the memory cell or the redundant cell. The timer measures the time elapsed from the start of the erase operation performed for the target cell by the erase circuit. The controller stops the erase operation and replaces the target cell with the redundant cell, when detecting that a predetermined time has elapsed from the start of the erase operation by the measurement of the elapsed time by the timer.

摘要翻译： 非易失性半导体存储器包括单元阵列，冗余阵列，擦除电路，定时器和控制器。 单元阵列具有多个存储单元。 冗余阵列具有能够替换存储单元的多个冗余单元。 擦除电路对包括存储单元或冗余单元的目标单元执行擦除操作。 定时器测量从擦除电路开始对目标单元执行的擦除操作所经过的时间。 当通过定时器测量经过的时间检测到从擦除操作开始经过了预定时间时，控制器停止擦除操作并且用冗余单元替换目标单元。

公开(公告)号：US20060067132A1

公开(公告)日：2006-03-30

申请号：US11213889

申请日：2005-08-30

申请人： Hiroshi Watanabe ,  Hideo Kato ,  Takamichi Kasai ,  Kiyomi Naruke ,  Hiroyuki Sasaki

发明人： Hiroshi Watanabe ,  Hideo Kato ,  Takamichi Kasai ,  Kiyomi Naruke ,  Hiroyuki Sasaki

IPC分类号： G11C16/04

CPC分类号： G11C16/3404

摘要： In a data erasing method of a nonvolatile semiconductor memory device, cells are subjected to the processings of executing programming by applying a voltage to the cells to set their threshold values at a given level or more, erasing the cells to set their threshold values at a lower level or less, executing weak programming once on a cell whose threshold value is lower than a further lower level, by applying a lower voltage to the cell, repeating the weak programming on the cell when its threshold value is still lower than the further lower level, until the value reaches the further lower level or more, verifying whether a cell is present whose threshold value is higher than the lower level, and returning the processing to the processing of setting the threshold values of the cells at the lower level or less, when verifying that the above cell is present.

摘要翻译： 在非易失性半导体存储器件的数据擦除方法中，通过向单元施加电压来对单元进行执行编程的处理，以将它们的阈值设置在给定等级或更多的值，擦除单元以将其阈值设置在 较低级别或更低级别，通过对小区施加较低的电压，在阈值低于更低级别的小区上执行弱编程一次，当其阈值仍然低于另一较低级别时，对小区重复弱编程 级，直到该值达到更低级别或更高级别，验证阈值是否高于较低级别的单元存在，并且将该处理返回到将小区的阈值设置为较低级别或更低级别的处理 ，当验证上述单元格是否存在时。

公开(公告)号：US06331948B2

公开(公告)日：2001-12-18

申请号：US09732478

申请日：2000-12-07

申请人： Takamichi Kasai ,  Nozomi Kasai

发明人： Takamichi Kasai ,  Nozomi Kasai

IPC分类号： G11C1606

CPC分类号： G11C16/3454

摘要： This invention provides a nonvolatile semiconductor memory device capable of avoiding complicatedness of algorithm for normal write operation and a write operation prior to erasing in a memory system in which the distribution of threshold of cells after erasing is adjusted. This nonvolatile semiconductor memory device generates check bits as error correction code according to a check bit generating matrix so formed that in both the normal write operation and the write operation prior to erasing, the factors of “1” of respective rows satisfy the quantity absolutely necessary for generating check bits and the quantity of the factors of “1” is an odd number.

摘要翻译： 本发明提供了一种非易失性半导体存储器件，其能够避免在擦除存储器系统中的正常写入操作和写入操作之间的写入操作的复杂性，其中调整了擦除之后的单元的阈值分布。 这种非易失性半导体存储器件根据形成的校验位产生矩阵产生作为纠错码的校验位，以便在擦除之前的正常写入操作和写入操作中，各行的“1”的因子满足绝对必要的量 用于产生检查位，并且因子“1”的数量是奇数。

公开(公告)号：US08331156B2

公开(公告)日：2012-12-11

申请号：US12882232

申请日：2010-09-15

申请人： Takamichi Kasai ,  Yoshiharu Hirata ,  Kazuaki Isobe ,  Akira Umezawa

发明人： Takamichi Kasai ,  Yoshiharu Hirata ,  Kazuaki Isobe ,  Akira Umezawa

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C16/30 ,  G11C16/0483 ,  G11C16/08

摘要： According to one embodiment, a nonvolatile semiconductor storage device includes a first well region of a first conductivity type, a second well region of the first conductivity type, a third well region of a second conductivity type, a bit line and a column decoder. A first cell array including a plurality of memory cells is formed in the first well region. A second cell array including a plurality of memory cells is formed in the second well region. The third well region includes the first and second well regions. The bit line is connected to the memory cells included in the first cell array and the memory cells included in the second cell array. The column decoder is connected to the bit line.

摘要翻译： 根据一个实施例，非易失性半导体存储装置包括第一导电类型的第一阱区，第一导电类型的第二阱区，第二导电类型的第三阱区，位线和列解码器。 在第一阱区中形成包括多个存储单元的第一单元阵列。 在第二阱区域中形成包括多个存储单元的第二单元阵列。 第三阱区域包括第一和第二阱区域。 位线连接到包括在第一单元阵列中的存储单元和包括在第二单元阵列中的存储单元。 列解码器连接到位线。

公开(公告)号：US20080056050A1

公开(公告)日：2008-03-06

申请号：US11846026

申请日：2007-08-28

申请人： Hideyoshi Takai ,  Takamichi Kasai

发明人： Hideyoshi Takai ,  Takamichi Kasai

IPC分类号： G11C8/00

CPC分类号： G11C8/10 ,  G11C29/02 ,  G11C29/024 ,  G11C29/18 ,  G11C2029/3602

摘要： A semiconductor memory device 100 is proposed including an internal address generation circuit 3, a first internal address control signal generation part 4, a second internal address control signal generation part 11, and an internal address control signal selection circuit 10 having an OR gate transistor 12. The internal address generation circuit 3 generates an internal address signal based on input address data. The first internal address control signal generation part 4 generates a first internal address control signal and having a function which fixes the first internal address control signal at a predetermined level with the elapse of a fixed period of time. The second internal address control signal generation part 11 generates a second internal address control signal corresponding to an input of a predetermined command. The OR gate transistor 12 transmits either the first internal address control signal or the second internal address control signal to the internal address generation circuit 3.

摘要翻译： 提出了一种半导体存储器件100，其包括内部地址产生电路3，第一内部地址控制信号产生部分4，第二内部地址控制信号产生部分11和具有或门晶体管12的内部地址控制信号选择电路10 。 内部地址生成电路3基于输入地址数据生成内部地址信号。 第一内部地址控制信号产生部分4产生第一内部地址控制信号，并且具有在经过一段固定时间段时将第一内部地址控制信号固定在预定电平的功能。 第二内部地址控制信号产生部分11产生与预定命令的输入相对应的第二内部地址控制信号。 或门晶体管12将第一内部地址控制信号或第二内部地址控制信号发送到内部地址产生电路3。

公开(公告)号：US08098532B2

公开(公告)日：2012-01-17

申请号：US12273813

申请日：2008-11-19

申请人： Yuji Komine ,  Shinya Fujisawa ,  Yasuhiko Honda ,  Ryu Hondai ,  Takamichi Kasai ,  Takahiro Suzuki

发明人： Yuji Komine ,  Shinya Fujisawa ,  Yasuhiko Honda ,  Ryu Hondai ,  Takamichi Kasai ,  Takahiro Suzuki

IPC分类号： G11C7/10

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C15/046 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/3454 ,  G11C16/3459

摘要： A non-volatile semiconductor storage device includes a memory cell array having a plurality of non-volatile memory cells, an address search circuit which searches for write object data and outputs an address where the write object data is present, when writing data into the non-volatile memory cells, and a control circuit which exercises control to write the write object data into the non-volatile memory cells in accordance with the address output from the address search circuit.

摘要翻译： 非挥发性半导体存储装置包括具有多个非易失性存储单元的存储单元阵列，地址搜索电路，当将数据写入非易失性存储单元时，搜索写入对象数据并输出存在写入对象数据的地址 并且控制电路根据从地址搜索电路输出的地址进行控制以将写入目标数据写入非易失性存储单元。