公开(公告)号：US06337268B1

公开(公告)日：2002-01-08

申请号：US09610701

申请日：2000-07-05

申请人： Shigenori Kido ,  Jiro Matsufusa ,  Tomoharu Mametani ,  Yoji Nakata ,  Takeshi Kishida ,  Yukihiro Nagai ,  Akinori Kinugasa ,  Hiroaki Nishimura

发明人： Shigenori Kido ,  Jiro Matsufusa ,  Tomoharu Mametani ,  Yoji Nakata ,  Takeshi Kishida ,  Yukihiro Nagai ,  Akinori Kinugasa ,  Hiroaki Nishimura

IPC分类号： H01L214763

CPC分类号： H01L21/76801 ,  H01L21/76804

摘要： A contact structure is formed with no voids in an interlayer insulation film and good surface planarity. A first insulation film (21) formed of p-TEOS is deposited to cover a substrate (1) and wires (4) formed on the substrate (1). A second insulation film (22) which is coating glass is formed by SOG. The surface is etched back from the opposite side to the substrate (1); therefore, the second insulation film (22) is etched. The etching is stopped at the point where the surface (21a) of the first insulation film (21) on the wires (4) is exposed. This ensures good surface,planarity. A third insulation film (23) is stacked on top of the second insulation film (22), and portions of the third insulation film (23) above the wires (4) are isotropically etched to form openings (51). At this time, the isotropic etching does not extend over the second insulation film (22).

摘要翻译： 在层间绝缘膜中形成没有空隙的接触结构和良好的表面平面度。 沉积由p-TEOS形成的第一绝缘膜（21）以覆盖基板（1）和形成在基板（1）上的布线（4）。 涂覆玻璃的第二绝缘膜（22）由SOG形成。 表面从衬底（1）的相对侧被回蚀刻; 因此，蚀刻第二绝缘膜（22）。 蚀刻停止在电线（4）上的第一绝缘膜（21）的表面（21a）露出的点处。 这确保了良好的表面，平坦度。 第三绝缘膜（23）层叠在第二绝缘膜（22）的顶部上，并且将各导线（4）上方的第三绝缘膜（23）的各部分各向同性地蚀刻以形成开口（51）。 此时，各向同性蚀刻不会延伸超过第二绝缘膜（22）。

公开(公告)号：US06787878B1

公开(公告)日：2004-09-07

申请号：US09631623

申请日：2000-08-04

申请人： Yukihiro Nagai ,  Tomoharu Mametani ,  Yoji Nakata ,  Shigenori Kido ,  Takeshi Kishida ,  Akinori Kinugasa ,  Hiroaki Nishimura ,  Jiro Matsufusa

发明人： Yukihiro Nagai ,  Tomoharu Mametani ,  Yoji Nakata ,  Shigenori Kido ,  Takeshi Kishida ,  Akinori Kinugasa ,  Hiroaki Nishimura ,  Jiro Matsufusa

IPC分类号： H01L2900

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a semiconductor device, an active region is formed in a semiconductor substrate separated by a plurality of isolation regions. A plurality of surface insulating films of different thickness are formed separately on the active region. A plurality of conductive films are formed on the respective insulating films. Then, one of the surface insulating film having smaller thickness is caused to break down to work as an electric fuse.

摘要翻译： 在半导体器件中，有源区形成在由多个隔离区隔开的半导体衬底中。 在活性区域上分别形成多个不同厚度的表面绝缘膜。 在各绝缘膜上形成多个导电膜。 然后，使具有较小厚度的表面绝缘膜中的一个分解成电熔丝。

公开(公告)号：US06313005B1

公开(公告)日：2001-11-06

申请号：US09610428

申请日：2000-07-05

申请人： Takeshi Kishida ,  Akinori Kinugasa ,  Yoji Nakata ,  Tomoharu Mametani ,  Shigenori Kido ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Jiro Matsufusa

发明人： Takeshi Kishida ,  Akinori Kinugasa ,  Yoji Nakata ,  Tomoharu Mametani ,  Shigenori Kido ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Jiro Matsufusa

IPC分类号： H01L2120

CPC分类号： H01L28/91 ,  H01L27/10855 ,  H01L28/84

摘要： Provided is a method of manufacturing a semiconductor device having a capacitor above a semiconductor substrate, with which it is possible to reduce the number of steps and the cost of manufacture. Specifically, a polysilicon layer (12) in which impurity is diffused is deposited on the entire surface including the inside of a hole (8A). An etching process of the polysilicon layer (12) is performed to form a storage node electrode composed of the polysilicon layer (12) remaining on the bottom and side of a groove for metallization (15) and in the hole (8A). The storage node electrode is broadly divided into a storage node electrode body disposed on the bottom and side of the groove for metallization (15), and a plug part disposed in the hole (8A). The storage node electrode is electrically connected via the plug part to a diffused region (19) of a semiconductor substrate (1).

摘要翻译： 提供一种制造半导体器件的方法，该半导体器件具有在半导体衬底上方的电容器，由此可以减少步骤数量和制造成本。 具体而言，在包括孔（8A）的内部的整个表面上沉积杂质扩散的多晶硅层（12）。 执行多晶硅层（12）的蚀刻工艺以形成由残留在金属化槽（15）的底部和侧面上的多晶硅层（12）和孔（8A）组成的存储节点电极。 存储节点电极大致分为设置在用于金属化的槽的底部和侧面上的存储节点电极体（15）和设置在孔（8A）中的插头部分。 存储节点电极经由插头部电连接到半导体衬底（1）的扩散区域（19）。

公开(公告)号：US06744143B1

公开(公告)日：2004-06-01

申请号：US09620718

申请日：2000-07-20

申请人： Jiro Matsufusa ,  Tomoharu Mametani ,  Takeshi Kishida ,  Yoji Nakata ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Akinori Kinugasa ,  Shigenori Kido

发明人： Jiro Matsufusa ,  Tomoharu Mametani ,  Takeshi Kishida ,  Yoji Nakata ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Akinori Kinugasa ,  Shigenori Kido

IPC分类号： H01L23544

CPC分类号： G03F7/70633 ,  H01L21/31612 ,  H01L23/544 ,  H01L2223/5442 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having a test mark comprising: a semiconductor substrate; a first TEOS layer formed on the semiconductor substrate; a second TEOS layer formed on the first TEOS layer and having a fluidity lower than that of the first TEOS layer at an elevated temperature; a recess formed in the first and second TEOS layers and exposing the surface of the semiconductor substrate, wherein the horizontal cross section of the recess is substantially rectangular in configuration; and a metal layer formed between the first and second TEOS layers and opposing to the corner of the recess.

摘要翻译： 一种具有测试标记的半导体器件，包括：半导体衬底; 形成在所述半导体衬底上的第一TEOS层; 形成在第一TEOS层上并且在升高的温度下具有低于第一TEOS层的流动性的第二TEOS层; 形成在所述第一和第二TEOS层中并且暴露所述半导体衬底的表面的凹部，其中所述凹部的水平横截面基本上为矩形; 以及形成在第一和第二TEOS层之间并且与凹部的拐角相对的金属层。

公开(公告)号：US06673671B1

公开(公告)日：2004-01-06

申请号：US09722479

申请日：2000-11-28

申请人： Hiroaki Nishimura ,  Tomoharu Mametani ,  Yukihiro Nagai ,  Akinori Kinugasa ,  Takeshi Kishida

发明人： Hiroaki Nishimura ,  Tomoharu Mametani ,  Yukihiro Nagai ,  Akinori Kinugasa ,  Takeshi Kishida

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： There is described a semiconductor device having a storage node capacitor structure suitable for rendering memory cells compact, and storage nodes are prevented from tilting. The device includes a storage node which has a vertical surface extending in the direction perpendicular to the surface of a semiconductor substrate, and a dielectric film for tilt prevention purposes which is brought into close contact with the side surface of the vertical surface and which prevents the vertical surface from tilting.

公开(公告)号：US06251741B1

公开(公告)日：2001-06-26

申请号：US09219786

申请日：1998-12-23

申请人： Akinori Kinugasa ,  Tomoharu Mametani ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Takeshi Kishida

发明人： Akinori Kinugasa ,  Tomoharu Mametani ,  Yukihiro Nagai ,  Hiroaki Nishimura ,  Takeshi Kishida

IPC分类号： H01L218242

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： There is described the manufacture of a semiconductor device having a storage node or high-yield manufacture of a compact memory IC. The present invention provides a method of manufacturing a semiconductor device including a basic dielectric layer formation step for forming a basic dielectric layer from a first dielectric material, a stopper film formation step for forming on the basic dielectric layer an etch stopper film from a second dielectric material differing from the first dielectric film, a sacrificial dielectric layer formation step for forming on the etch stopper film a sacrificial dielectric layer from the first dielectric material, a space formation step for forming a storage node formation space by removal of a predetermined area from the sacrificial dielectric layer until the etch stopper film becomes exposed, a storage node formation step for forming in the storage node formation space a storage node from a capacitive material, and a sacrificial dielectric layer removal step for removing the sacrificial dielectric layer surrounding the storage node by means of an etching operation suitable for removal of the first dielectric material.

摘要翻译： 描述了具有存储节点或紧凑型存储器IC的高产量制造的半导体器件的制造。 本发明提供一种制造半导体器件的方法，该半导体器件包括用于从第一介电材料形成基本电介质层的基本电介质层形成步骤，用于在基本电介质层上形成来自第二电介质的蚀刻停止膜的阻挡膜形成步骤 与第一介电膜不同的材料;牺牲介电层形成步骤，用于在蚀刻停止膜上形成来自第一介电材料的牺牲介电层;空间形成步骤，用于通过从第一电介质膜去除预定区域形成存储节点形成空间; 牺牲电介质层，直到蚀刻停止膜露出，存储节点形成步骤，用于在存储节点形成空间中形成存储节点与电容材料;以及牺牲介电层去除步骤，用于通过以下步骤去除存储节点周围的牺牲介电层： 蚀刻操作的手段适合于去除 l的第一介电材料。

公开(公告)号：US07829983B2

公开(公告)日：2010-11-09

申请号：US11997700

申请日：2006-07-28

申请人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

发明人： Yutaka Yamada ,  Takeshi Kishida ,  Yoshikazu Tamura ,  Yasuo Sogawa ,  Masanori Hirofuji

IPC分类号： H01L23/495

CPC分类号： H01L24/06 ,  H01L23/50 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48599 ,  H01L2224/49113 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49431 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/3011 ,  H01L2224/78 ,  H01L2924/00

摘要： There is provided a semiconductor device adopting, as a layout of pads connected to an external package on an LSI, a zigzag pad layout in which the pads are arranged shifted alternately, which can avoid occurrences of short-circuiting of wires, an increase in chip size due to avoidance of short-circuiting, propagation of power supply or GND noise due to reduction in IO cell interval, and signal transmission delay difference due to displacement of pad positions. In a semiconductor device wherein plural pads on a semiconductor element which are connected to function terminals on an external package are arranged in two lines along the periphery of the semiconductor element, an arrangement order of the plural pads on the semiconductor element is different from an arrangement order of the function terminals on the external package.

摘要翻译： 提供了一种半导体器件，其采用连接到LSI上的外部封装的焊盘的布局，其中焊盘布置移位的之字形焊盘布局，这可以避免导线短路的发生，芯片的增加 由于避免短路，由于IO单元间隔的减少而导致的电源传播或GND噪声，以及由于焊盘位置的位移引起的信号传输延迟差异。 在半导体装置中，与外部封装上的功能端子连接的半导体元件上的多个焊盘沿着半导体元件的周边配置成两列，半导体元件上的多个焊盘的配置顺序与布置 外部封装上功能端子的顺序。

公开(公告)号：US08564037B2

公开(公告)日：2013-10-22

申请号：US13012305

申请日：2011-01-24

申请人： Takeshi Kishida

发明人： Takeshi Kishida

IPC分类号： H01L27/108

CPC分类号： H01L21/76224 ,  H01L29/06

摘要： A semiconductor device may include, but is not limited to, a semiconductor substrate having a device isolation groove defining first to fourth device formation portions. The second device formation portion is separated from the first device formation portion. The third device formation portion extends from the first device formation portion. The third device formation portion is separated from the second device formation portion. The fourth device formation portion extends from the second device formation portion. The fourth device formation portion is separated from the first and third device formation portions. The third and fourth device formation portions are positioned between the first and second device formation portions.

摘要翻译： 半导体器件可以包括但不限于具有限定第一至第四器件形成部分的器件隔离槽的半导体衬底。 第二装置形成部分与第一装置形成部分分离。 第三装置形成部分从第一装置形成部分延伸。 第三装置形成部分与第二装置形成部分分离。 第四装置形成部分从第二装置形成部分延伸。 第四装置形成部分与第一和第三装置形成部分分离。 第三和第四装置形成部分位于第一和第二装置形成部分之间。

公开(公告)号：US07194602B2

公开(公告)日：2007-03-20

申请号：US10385854

申请日：2003-03-12

申请人： Takeshi Kishida ,  Masaitsu Nakajima

发明人： Takeshi Kishida ,  Masaitsu Nakajima

IPC分类号： G06F9/34 ,  G06F9/355

CPC分类号： G06F9/30149 ,  G06F9/3013 ,  G06F9/30138 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/3822 ,  G06F9/384 ,  G06F9/3853

摘要： A data processor according to the present invention executes instructions described in first and second instruction formats. The first instruction format defines a register-addressing field of a predetermined size, while the second instruction format defines a register-addressing field of a size larger than that of the register-addressing field defined by the first instruction format. The data processor includes: instruction-type identifier, responsive to an instruction, for identifying the received instruction as being described in the first or second instruction format by the instruction itself; a first register file including a plurality of registers; and a second register file also including a plurality of registers, the number of the registers included in the second register file being larger than that of the registers included in the first register file. If the instruction-type identifier has identified the received instruction as being described in the first instruction format, the data processor executes the instruction using data held in the first register file. On the other hand, if the instruction-type identifier has identified the received instruction as being described in the second instruction format, the data processor executes the instruction using data held in the second register file.

摘要翻译： 根据本发明的数据处理器执行以第一和第二指令格式描述的指令。 第一指令格式定义了预定大小的寄存器寻址字段，而第二指令格式定义了大于由第一指令格式定义的寄存器寻址字段的大小的寄存器寻址字段。 数据处理器包括：指令类型标识符，响应于指令，用于通过指令本身识别接收到的以第一或第二指令格式描述的指令; 包括多个寄存器的第一寄存器堆; 以及还包括多个寄存器的第二寄存器堆，包括在第二寄存器堆中的寄存器的数目大于包含在第一寄存器堆中的寄存器的寄存器数。 如果指令类型标识符已经将接收到的指令识别为如第一指令格式所描述的那样，则数据处理器使用保存在第一寄存器文件中的数据来执行指令。 另一方面，如果指令类型标识符已经将接收到的指令识别为如第二指令格式所描述的那样，则数据处理器使用保存在第二寄存器堆中的数据来执行指令。

公开(公告)号：US06977199B2

公开(公告)日：2005-12-20

申请号：US10900151

申请日：2004-07-28

申请人： Takeshi Kishida ,  Yusuke Kawase

发明人： Takeshi Kishida ,  Yusuke Kawase

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/84

摘要： On a silicon oxide film including the interior of an opening a semispherical RGP film is deposited. At a temperature lower than that allowing a crystal of silicon to be grown a BPTEOS film is deposited to fill the opening. Then a portion other than the semispherical RGP film introduced in the opening is chemically mechanically polished and thus removed. This contributes to reduced crystal growth of silicon at the semispherical RGP film and hence reduced scattering and/or removal of the RGP film for example when a CMP step is performed. Subsequently the semispherical RGP film is annealed to grow a crystal of silicon to form a generally spherical RGP film. Thus a storage node can have an increased surface area and a capacitor can have increased capacity.

摘要翻译： 在包含开口内部的氧化硅膜上沉积半球形RGP膜。 在低于允许生长硅晶体的温度下，沉积BPTEOS膜以填充开口。 然后将引入到开口中的半球形RGP膜以外的部分化学机械抛光并因此被除去。 这有助于在半球形RGP膜处降低硅的晶体生长，并因此例如当执行CMP步骤时减少RGP膜的散射和/或去除。 随后将半球形RGP膜退火以生长硅晶体，以形成通常为球形的RGP膜。 因此，存储节点可以具有增加的表面积，并且电容器可以具有增加的容量。