公开(公告)号：US08619474B2

公开(公告)日：2013-12-31

申请号：US12556941

申请日：2009-09-10

申请人： Akira Goda ,  Andrew Bicksler ,  Violante Moschiano ,  Giuseppina Puzzilli

发明人： Akira Goda ,  Andrew Bicksler ,  Violante Moschiano ,  Giuseppina Puzzilli

IPC分类号： G11C7/02

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C2211/5621

摘要： Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.

摘要翻译： 公开了存储器件和方法，例如被配置为在程序操作的第一部分期间向数据线施加第一程序禁止偏置的器件，并且在程序操作的第二部分期间对数据线施加第二程序禁止偏置。 第二个程序禁止偏置大于第一个程序抑制偏置。

公开(公告)号：US08514624B2

公开(公告)日：2013-08-20

申请号：US13165416

申请日：2011-06-21

申请人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

发明人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC分类号： G11C16/04

CPC分类号： G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

摘要： Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

摘要翻译： 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US08369158B2

公开(公告)日：2013-02-05

申请号：US12646136

申请日：2009-12-23

申请人： Akira Goda ,  Giuseppina Puzzilli

发明人： Akira Goda ,  Giuseppina Puzzilli

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.

摘要翻译： 配置为执行擦除操作的擦除操作和装置适用于具有排列成串的存储单元的非易失性存储器件。 一种这样的方法包括将一串存储器单元的选择栅极控制线偏置到第一偏置电位，将一对存储器单元的访问线偏置到第二偏置电位，并将一个或多个剩余存储器单元的访问线偏置到第三偏置电位 潜在。 斜坡偏置电位基本上与偏置选择栅极控制线和接入线的同时或之后施加到存储器单元串的沟道区，并且响应于斜坡偏置电位达到释放偏压而浮动选择栅极控制线 斜坡偏置电位的初始偏置电位与斜坡偏置电位的目标偏置电位之间的电位。

公开(公告)号：US20120327713A1

公开(公告)日：2012-12-27

申请号：US13165416

申请日：2011-06-21

申请人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

发明人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

摘要： Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

摘要翻译： 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US20110199827A1

公开(公告)日：2011-08-18

申请号：US12707162

申请日：2010-02-17

申请人： Giuseppina Puzzilli ,  Andrew Bicksler ,  Akira Goda

发明人： Giuseppina Puzzilli ,  Andrew Bicksler ,  Akira Goda

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C11/5628 ,  G11C16/0483

摘要： Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

摘要翻译： 记忆及其记忆阵列被公开。 一个这样的存储器阵列具有一串串联耦合的存储器单元，串联耦合到串联耦合存储器单元串的第一端的非可编程选择栅极，以及串联耦合到第二端的可编程选择栅极 串联的存储单元串。

公开(公告)号：US08228735B2

公开(公告)日：2012-07-24

申请号：US12707162

申请日：2010-02-17

申请人： Giuseppina Puzzilli ,  Andrew Bicksler ,  Akira Goda

发明人： Giuseppina Puzzilli ,  Andrew Bicksler ,  Akira Goda

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/0483

摘要： Memories and their memory arrays are disclosed. One such memory array has a string of series-coupled memory cells, a non-programmable select gate coupled in series to a first end of the string of series-coupled memory cells, and a programmable select gate coupled in series to a second end of the string of series-coupled memory cells.

摘要翻译： 记忆及其记忆阵列被公开。 一个这样的存储器阵列具有一串串联耦合的存储器单元，串联耦合到串联耦合存储器单元串的第一端的非可编程选择栅极，以及串联耦合到第二端的可编程选择栅极 串联的存储单元串。

公开(公告)号：US20110149659A1

公开(公告)日：2011-06-23

申请号：US12646136

申请日：2009-12-23

申请人： Akira Goda ,  Giuseppina Puzzilli

发明人： Akira Goda ,  Giuseppina Puzzilli

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/16

摘要： Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.

摘要翻译： 配置为执行擦除操作的擦除操作和装置适用于具有排列成串的存储单元的非易失性存储器件。 一种这样的方法包括将一串存储器单元的选择栅极控制线偏置到第一偏置电位，将一对存储器单元的访问线偏置到第二偏置电位，并将一个或多个剩余存储器单元的访问线偏置到第三偏置电位 潜在。 斜坡偏置电位基本上与偏置选择栅极控制线和接入线的同时或之后施加到存储器单元串的沟道区，并且响应于斜坡偏置电位达到释放偏压而浮动选择栅极控制线 斜坡偏置电位的初始偏置电位与斜坡偏置电位的目标偏置电位之间的电位。

公开(公告)号：US20110058424A1

公开(公告)日：2011-03-10

申请号：US12556941

申请日：2009-09-10

申请人： Akira Goda ,  Andrew Bicksler ,  Violante Moschiano ,  Giuseppina Puzzilli

发明人： Akira Goda ,  Andrew Bicksler ,  Violante Moschiano ,  Giuseppina Puzzilli

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3418 ,  G11C2211/5621

摘要： Memory devices and methods are disclosed, such as devices configured to apply a first program inhibit bias to data lines during a first portion of a program operation and to apply a second program inhibit bias to data lines during a second portion of the program operation. The second program inhibit bias is greater than the first program inhibit bias.

摘要翻译： 公开了存储器件和方法，例如被配置为在程序操作的第一部分期间向数据线施加第一程序禁止偏置的器件，并且在程序操作的第二部分期间对数据线施加第二程序禁止偏置。 第二个程序禁止偏置大于第一个程序抑制偏置。

公开(公告)号：US10541029B2

公开(公告)日：2020-01-21

申请号：US13564458

申请日：2012-08-01

申请人： Peter Sean Feeley ,  Koji Sakui ,  Akira Goda

发明人： Peter Sean Feeley ,  Koji Sakui ,  Akira Goda

IPC分类号： G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.

公开(公告)号：US20180286483A1

公开(公告)日：2018-10-04

申请号：US15477048

申请日：2017-04-01

申请人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

发明人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C8/08

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621

摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.