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    Floating gate structures
    4.
    发明授权
    Floating gate structures 有权
    浮门结构

    公开(公告)号：US07989289B2

    公开(公告)日：2011-08-02

    申请号：US12165272

    申请日：2008-06-30

    申请人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

    发明人： Tejas Krishnamohan ,  Krishna Parat ,  Kyu Min ,  Srivardhan Gowda ,  Thomas M. Graettinger ,  Nirmal Ramaswamy

    IPC分类号： H01L21/336 ,  H01L29/788

    CPC分类号： H01L21/28052 ,  H01L21/28273 ,  H01L29/66825 ,  H01L29/7881

    摘要： Floating gate structures are generally described. In one example, an electronic device includes a semiconductor substrate, a tunnel dielectric coupled with the semiconductor substrate, and a floating gate structure comprising at least a first region having a first electron energy level or electron workfunction or carrier capture efficiency coupled with the tunnel dielectric and a second region having a second electron energy level or electron workfunction or carrier capture efficiency coupled with the first region wherein the first electron energy level or electron workfunction or carrier capture efficiency is less than the second electron energy level or electron workfunction or carrier capture efficiency. Such electronic device may reduce the thickness of the floating gate structure or reduce leakage current through an inter-gate dielectric, or combinations thereof, compared with a floating gate structure that comprises only polysilicon.

    摘要翻译： 通常描述浮栅结构。 在一个示例中，电子设备包括半导体衬底，与半导体衬底耦合的隧道电介质，以及浮栅结构，其至少包括具有第一电子能级或电子功函数的第一区域或与隧道电介质耦合的载流子捕获效率 以及第二区域，其具有与第一区域耦合的第二电子能级或电子功能函数或载流子捕获效率，其中第一电子能级或电子功函数或载流子捕获效率小于第二电子能级或电子功函数或载流子俘获效率 。 与仅包含多晶硅的浮动栅极结构相比，这种电子器件可以减小浮置栅极结构的厚度或减小通过栅极间电介质或其组合的泄漏电流。

    Memory Cells
    5.
    发明申请
    Memory Cells 有权
    记忆细胞

    公开(公告)号：US20110133268A1

    公开(公告)日：2011-06-09

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D.V. Nirmal Ramaswamy ,  Ronald A. Weimer ,  Arup Bhattacharyya

    IPC分类号： H01L29/792

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。

    Semiconductor device with high on current and low leakage
    6.
    发明授权
    Semiconductor device with high on current and low leakage 失效
    半导体器件具有高导通电流和低漏电流

    公开(公告)号：US07728387B1

    公开(公告)日：2010-06-01

    申请号：US11761830

    申请日：2007-06-12

    申请人： Tejas Krishnamohan ,  Krishna Chandra Saraswat

    发明人： Tejas Krishnamohan ,  Krishna Chandra Saraswat

    IPC分类号： H01L31/119

    CPC分类号： H01L29/1054 ,  H01L29/78

    摘要： Various semiconductor devices and methods of manufacture are employed. According to an example embodiment of the present invention, a MOS-compatible semiconductor device exhibits high channel mobility and low leakage. The device includes a channel region having a high-mobility strained material layer and a tunneling mitigation layer on the strained material layer to mitigate tunnel leakage. The strained material has a lattice structure that is strained to match the lattice structure of the tunneling mitigation layer. An insulator layer is on the tunneling mitigation layer, and an electrode is over the insulator and adapted to apply a voltage bias to the channel region to switch the device between conductive and nonconductive states. Current is transported in the conductive state as predominantly facilitated via the mobility of the strained material layer, and wherein tunneling current in the nonconductive state is mitigated by the tunneling mitigation layer.

    摘要翻译： 采用各种半导体器件和制造方法。 根据本发明的示例性实施例，MOS兼容半导体器件表现出高的沟道迁移率和低的泄漏。 该装置包括在应变材料层上具有高迁移率应变材料层和隧道缓解层的沟道区，以减轻隧道泄漏。 应变材料具有应变以匹配隧道缓解层的晶格结构的晶格结构。 绝缘体层位于隧道缓解层上，并且电极在绝缘体上方并且适于向通道区域施加电压偏置，以在导电状态和非导通状态之间切换器件。 电流以导电状态传输，主要通过应变材料层的迁移率促进，并且其中非导电状态的隧穿电流被隧道缓解层减轻。

    Memory cells containing charge-trapping zones
    7.
    发明授权
    Memory cells containing charge-trapping zones 有权
    含有电荷捕获区的存储单元

    公开(公告)号：US08228743B2

    公开(公告)日：2012-07-24

    申请号：US13024903

    申请日：2011-02-10

    申请人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A Weimer ,  Arup Bhattacharyya

    发明人： Kyu S. Min ,  Rhett T. Brewer ,  Tejas Krishnamohan ,  Thomas M. Graettinger ,  D. V. Nirmal Ramaswamy ,  Ronald A Weimer ,  Arup Bhattacharyya

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  B82Y10/00 ,  G11C11/5671 ,  G11C16/0475 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/42348 ,  Y10S977/943

    摘要： Some embodiments include memory cells having vertically-stacked charge-trapping zones spaced from one another by dielectric material. The dielectric material may comprise high-k material. One or more of the charge-trapping zones may comprise metallic material. Such metallic material may be present as a plurality of discrete isolated islands, such as nanodots. Some embodiments include methods of forming memory cells in which two charge-trapping zones are formed over tunnel dielectric, with the zones being vertically displaced relative to one another, and with the zone closest to the tunnel dielectric having deeper traps than the other zone. Some embodiments include electronic systems comprising memory cells. Some embodiments include methods of programming memory cells having vertically-stacked charge-trapping zones.

    摘要翻译： 一些实施例包括具有通过介电材料彼此间隔开的垂直堆叠的电荷捕获区的存储单元。 电介质材料可以包括高k材料。 一个或多个电荷捕获区可以包括金属材料。 这种金属材料可以作为多个离散的隔离岛存在，例如纳米点。 一些实施例包括形成存储器单元的方法，其中在隧道电介质上形成两个电荷捕获区，其中区域相对于彼此垂直位移，并且最靠近隧道电介质的区域具有比另一区更深的陷阱。 一些实施例包括包括存储器单元的电子系统。 一些实施例包括编程具有垂直堆叠的电荷捕获区的存储器单元的方法。