公开(公告)号：US08355275B2

公开(公告)日：2013-01-15

申请号：US13239899

申请日：2011-09-22

Applicant: Reika Ichihara ,  Akira Takashima

Inventor： Reika Ichihara ,  Akira Takashima

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/76

Abstract: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C

Abstract translation: 根据一个实施例，电阻变化存储器包括：串联连接的包括电阻变化元件和堆叠层结构的存储单元;控制电路，被配置为控制将电阻变化元件从第一电阻值改变到 第二电阻值低于第一电阻值;以及电压脉冲发生电路，被配置为在第一操作中产生要施加到存储单元的第一电压脉冲。 堆叠层结构包括两个导电层和形成在两个导电层之间的绝缘层。 第一电压脉冲的振幅在第一电压区域中，其中堆叠层结构用作电容器。 第一电压脉冲满足Ron×C

公开(公告)号：US08331137B2

公开(公告)日：2012-12-11

申请号：US13234796

申请日：2011-09-16

Applicant: Akira Takashima ,  Reika Ichihara

Inventor： Akira Takashima ,  Reika Ichihara

IPC: G11C11/00

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/76

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括存储单元，其包括可变电阻元件和串联连接在第一和第二导线之间的电容器，以及将第一和第二电压脉冲之一施加到存储单元的控制电路。 电容器由第一和第二电压脉冲之一的前沿充电，并且将第一和第二电压脉冲之一的后沿放电。 控制电路使得第一和第二电压脉冲的后沿的波形不同，通过使用第一电压脉冲将可变电阻元件的电阻值从第一电阻值改变为第二电阻值，并且改变电阻值 通过使用第二电压脉冲从第二电阻值到第一电阻值。

公开(公告)号：US07863695B2

公开(公告)日：2011-01-04

申请号：US12200599

申请日：2008-08-28

Applicant: Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

Inventor： Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823857 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/785

Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.

Abstract translation: 互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管 形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管， 以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

公开(公告)号：US20090114995A1

公开(公告)日：2009-05-07

申请号：US12200599

申请日：2008-08-28

Applicant: Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

Inventor： Masamichi Suzuki ,  Masato Koyama ,  Yoshinori Tsuchiya ,  Hirotaka Nishino ,  Reika Ichihara ,  Akira Takashima

IPC: H01L27/08 ,  H01L21/3205

CPC classification number: H01L21/823857 ,  H01L21/26506 ,  H01L21/31155 ,  H01L21/823842 ,  H01L29/517 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7842 ,  H01L29/7846 ,  H01L29/785

Abstract: A complementary semiconductor device includes a semiconductor substrate, a first semiconductor region formed on a surface of the semiconductor substrate, a second semiconductor region formed on the surface of the semiconductor substrate apart from the first semiconductor region, an n-MIS transistor having a first gate insulating film including La and Al, formed on the first semiconductor region, and a first gate electrode formed on the gate insulating film, and a p-MIS transistor having a second gate insulating film including La and Al, formed on the second semiconductor region, and a second gate electrode formed on the gate insulating film, an atomic density ratio Al/La in the second gate insulating film being larger than an atomic density ratio Al/La in the first gate insulating film.

Abstract translation: 互补半导体器件包括半导体衬底，形成在半导体衬底的表面上的第一半导体区域，形成在半导体衬底的离开第一半导体区域的表面上的第二半导体区域，具有第一栅极的n-MIS晶体管 形成在第一半导体区域上的包括La和Al的绝缘膜和形成在栅极绝缘膜上的第一栅电极和形成在第二半导体区上的具有包括La和Al的第二栅极绝缘膜的p-MIS晶体管， 以及形成在所述栅极绝缘膜上的第二栅电极，所述第二栅极绝缘膜中的原子密度比Al / La大于所述第一栅极绝缘膜中的原子密度比Al / La。

公开(公告)号：US20120250394A1

公开(公告)日：2012-10-04

申请号：US13239899

申请日：2011-09-22

Applicant: Reika Ichihara ,  Akira Takashima

Inventor： Reika Ichihara ,  Akira Takashima

IPC: G11C11/21

CPC classification number: G11C13/0007 ,  G11C13/003 ,  G11C2213/76

Abstract: According to one embodiment, a resistance change memory includes a memory cell including a resistance change element and a stacked layer structure which are connected in series, a control circuit configured to control a first operation of changing the resistance change element from a first resistance value to a second resistance value lower than the first resistance value, and a voltage pulse generating circuit configured to generate a first voltage pulse to be applied to the memory cell in the first operation. The stacked layer structure includes two conductive layers and an insulating layer formed between the two conductive layers. Amplitude of the first voltage pulse is in a first voltage area in which the stacked layer structure functions as a capacitor. The first voltage pulse satisfies Ron×C

Abstract translation: 根据一个实施例，电阻变化存储器包括：串联连接的包括电阻变化元件和堆叠层结构的存储单元;控制电路，被配置为控制将电阻变化元件从第一电阻值改变到 第二电阻值低于第一电阻值;以及电压脉冲发生电路，被配置为在第一操作中产生要施加到存储单元的第一电压脉冲。 堆叠层结构包括两个导电层和形成在两个导电层之间的绝缘层。 第一电压脉冲的振幅在第一电压区域中，其中堆叠层结构用作电容器。 第一电压脉冲满足Ron×C

公开(公告)号：US20120243293A1

公开(公告)日：2012-09-27

申请号：US13234796

申请日：2011-09-16

Applicant: Akira TAKASHIMA ,  Reika Ichihara

Inventor： Akira TAKASHIMA ,  Reika Ichihara

IPC: G11C11/21

CPC classification number: G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C13/0097 ,  G11C2013/0092 ,  G11C2213/33 ,  G11C2213/76

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a memory cell includes a variable resistance element and a capacitor connected in series between first and second conductive lines, and a control circuit applying one of first and second voltage pulses to the memory cell. The capacitor is charged by a leading edge of one of the first and second voltage pulses, and discharged a trailing edge of one of the first and second voltage pulses. The control circuit makes waveforms of the trailing edges of the first and second voltage pulses be different, changes a resistance value of the variable resistance element from a first resistance value to a second resistance value by using the first voltage pulse, and changes the resistance value of the variable resistance element from the second resistance value to the first resistance value by using the second voltage pulse.

Abstract translation: 根据一个实施例，非易失性半导体存储器件包括存储单元，其包括可变电阻元件和串联连接在第一和第二导线之间的电容器，以及将第一和第二电压脉冲之一施加到存储单元的控制电路。 电容器由第一和第二电压脉冲之一的前沿充电，并且将第一和第二电压脉冲之一的后沿放电。 控制电路使得第一和第二电压脉冲的后沿的波形不同，通过使用第一电压脉冲将可变电阻元件的电阻值从第一电阻值改变为第二电阻值，并且改变电阻值 通过使用第二电压脉冲从第二电阻值到第一电阻值。

公开(公告)号：US08988925B2

公开(公告)日：2015-03-24

申请号：US13597318

申请日：2012-08-29

Applicant: Reika Ichihara ,  Takayuki Tsukamoto

Inventor： Reika Ichihara ,  Takayuki Tsukamoto

IPC: G11C11/00 ,  G11C13/00

CPC classification number: G11C11/00 ,  G11C2013/0083

Abstract: A nonvolatile semiconductor memory device in accordance with an embodiment comprises a plurality of first, second lines, a plurality of memory cells, and a control circuit. The plurality of second lines extend so as to intersect the first lines. The plurality of memory cells are disposed at intersections of the first, second lines, and each includes a variable resistor. The control circuit is configured to control a voltage applied to the memory cells. The control circuit applies a first pulse voltage to the variable resistor during a forming operation. In addition, the control circuit applies a second pulse voltage to the variable resistor during a setting operation, the second pulse voltage having a polarity opposite to the first pulse voltage. Furthermore, the control circuit applies a third pulse voltage to the variable resistor during a resetting operation, the third pulse voltage having a polarity identical to the first pulse voltage.

Abstract translation: 根据实施例的非易失性半导体存储器件包括多个第一，第二线，多个存储单元和控制电路。 多个第二线延伸以与第一线相交。 多个存储单元设置在第一和第二线的交点处，并且每个都包括可变电阻器。 控制电路被配置为控制施加到存储器单元的电压。 控制电路在成形操作期间向可变电阻器施加第一脉冲电压。 此外，控制电路在设定操作期间向可变电阻施加第二脉冲电压，第二脉冲电压具有与第一脉冲电压相反的极性。 此外，控制电路在复位操作期间向可变电阻器施加第三脉冲电压，第三脉冲电压具有与第一脉冲电压相同的极性。

公开(公告)号：US08698277B2

公开(公告)日：2014-04-15

申请号：US13233623

申请日：2011-09-15

Applicant: Takashi Yamauchi ,  Shosuke Fujii ,  Reika Ichihara

Inventor： Takashi Yamauchi ,  Shosuke Fujii ,  Reika Ichihara

IPC: H01L23/52 ,  H01L29/00 ,  H01L47/00 ,  H01L29/02 ,  H01L29/04 ,  H01L29/06 ,  G11C11/00

CPC classification number: H01L45/1253 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/085 ,  H01L45/148 ,  H01L45/1616 ,  H01L45/1641

Abstract: According to one embodiment, a nonvolatile variable resistance device includes a first electrode, a second electrode, a first layer, and a second layer. The second electrode includes a metal element. The first layer is arranged between the first electrode and the second electrode and includes a semiconductor element. The second layer is inserted between the second electrode and the first layer and includes the semiconductor element. The percentage of the semiconductor element being unterminated is higher in the second layer than in the first layer.

Abstract translation: 根据一个实施例，非易失性可变电阻器件包括第一电极，第二电极，第一层和第二层。 第二电极包括金属元件。 第一层布置在第一电极和第二电极之间，并且包括半导体元件。 第二层插入在第二电极和第一层之间并且包括半导体元件。 未终止的半导体元件的百分比在第二层比在第一层中高。

公开(公告)号：US08410556B2

公开(公告)日：2013-04-02

申请号：US13290552

申请日：2011-11-07

Applicant: Reika Ichihara ,  Masato Koyama

Inventor： Reika Ichihara ,  Masato Koyama

IPC: H01L29/78 ,  H01L29/43

CPC classification number: H01L27/092 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/518 ,  H01L29/6659

Abstract: A semiconductor device includes pMISFET and nMIS formed on the semiconductor substrate. The pMISFET includes, on the semiconductor substrate, first source/drain regions, a first gate dielectric formed therebetween, first lower and upper metal layers stacked on the first gate dielectric, a first upper metal layer containing at least one metallic element belonging to groups IIA and IIIA. The nMISFET includes, on the semiconductor substrate, second source/drain regions, second gate dielectric formed therebetween, a second lower and upper metal layers stacked on the second gate dielectric and the second upper metal layer substantially having the same composition as the first upper metal layer. The first lower metal layer is thicker than the second lower metal layer, and the atomic density of the metallic element contained in the first gate dielectric is lower than the atomic density of the metallic element contained in the second gate dielectric.

Abstract translation: 半导体器件包括在半导体衬底上形成的pMISFET和nMIS。 pMISFET在半导体衬底上包括第一源极/漏极区域，在其间形成的第一栅极电介质，堆叠在第一栅极电介质上的第一下部和上部金属层，包含至少一个属于IIA族金属元素的第一上部金属层 和IIIA。 nMISFET在半导体衬底上包括第二源极/漏极区域，在其间形成的第二栅极电介质，堆叠在第二栅极电介质上的第二下部和上部金属层，以及基本上具有与第一上部金属相同的组成的第二上部金属层 层。 第一下金属层比第二下金属层厚，并且包含在第一栅极电介质中的金属元素的原子密度低于包含在第二栅极电介质中的金属元素的原子密度。

公开(公告)号：US08324606B2

公开(公告)日：2012-12-04

申请号：US12563470

申请日：2009-09-21

Applicant: Takayuki Tsukamoto ,  Reika Ichihara ,  Hiroshi Kanno ,  Kenichi Murooka

Inventor： Takayuki Tsukamoto ,  Reika Ichihara ,  Hiroshi Kanno ,  Kenichi Murooka

IPC: H01L47/00

CPC classification number: G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2213/72 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/2481

Abstract: A resistance change type memory of an aspect of the present invention including a first wiring configured to extend in a first direction, a second wiring configured to extend in a second direction crossing the first direction, a series circuit configured to connect to the first and second wirings, the series circuit including a non-ohmic element being more conductive in the first to second wiring direction than in the second to first direction and a resistance change type storage element in which data is stored according to a change of a resistance state, an energy supplying circuit configured to connect to the first wiring to supply energy to the first wiring, the energy being used to store the data in the resistance change type storage element, and a capacitance circuit configured to include a capacitive element and being connected to the second wiring.

Abstract translation: 本发明的一个方面的电阻变化型存储器包括：构造成沿第一方向延伸的第一布线，沿与第一方向交叉的第二方向延伸的第二布线;串联电路，被配置为连接到第一和第二端 布线，包括在第一至第二布线方向上比在第二至第一方向上更加导电的非欧姆元件的串联电路和根据电阻状态的变化存储数据的电阻变化型存储元件， 能量供给电路，被配置为连接到所述第一布线以向所述第一布线供应能量，所述能量用于将所述数据存储在所述电阻变化型存储元件中;以及电容电路，被配置为包括电容元件并连接到所述第二布线 接线。