公开(公告)号：US07084043B2

公开(公告)日：2006-08-01

申请号：US10792691

申请日：2004-03-05

申请人： Albert Birner ,  Steffen Breuer ,  Matthias Goldbach ,  Joern Luetzen ,  Dirk Schumann

发明人： Albert Birner ,  Steffen Breuer ,  Matthias Goldbach ,  Joern Luetzen ,  Dirk Schumann

IPC分类号： H01L21/76 ,  H01L21/31

CPC分类号： H01L27/10864 ,  H01L27/10867 ,  H01L27/1203

摘要： A method for producing a silicon-on-insulator layer structure on a silicon surface with any desired geometry can locally produce the silicon-on-insulator structure. The method includes formation of mesopores in the silicon surface region, oxidation of the mesopore surface to form silicon oxide and rib regions from silicon in single-crystal form; and execution of a selective epitaxy process that that silicon grows on the uncovered rib regions, selectively with respect to the silicon oxide regions. Rib regions remain in place between adjacent mesopores, this step being ended as soon as a predetermined minimum silicon wall thickness of the rib regions is reached, the uncovering of the rib regions, which are arranged at the end remote from the semiconductor substrate between adjacent mesopores. The method can be used to fabricate a vertical transistor and a memory cell having a select transistor of this type.

摘要翻译： 在任何期望的几何形状的硅表面上制造绝缘体上硅层结构的方法可以局部地产生绝缘体上硅结构。 该方法包括在硅表面区域形成中孔，中孔表面的氧化形成硅单晶的硅氧化物和肋状区域; 以及执行选择性外延工艺，其中硅在相对于氧化硅区域选择性地在未覆盖的肋区域上生长。 肋区域保持在相邻的中孔之间的适当位置，一旦达到肋区域的预定的最小硅壁厚度，则该步骤结束，肋区域的露出，其布置在远离半导体衬底的相邻介孔之间的端部 。 该方法可用于制造具有这种类型的选择晶体管的垂直晶体管和存储单元。

公开(公告)号：US07208370B2

公开(公告)日：2007-04-24

申请号：US10484562

申请日：2002-07-08

申请人： Albert Birner ,  Joern Luetzen

发明人： Albert Birner ,  Joern Luetzen

IPC分类号： H01L21/8242

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L27/10867 ,  H01L27/10876 ,  H01L29/66666

摘要： To fabricate a vertical transistor, a trench is provided, the side wall of which is formed by a semiconductor substrate in single crystal form and the base of which is formed by a polycrystalline semiconductor substrate. A transition region is arranged between the side wall and the base. A semiconductor layer is deposited so that an epitaxial semiconductor layer grows on the side wall and a semiconductor layer grows on the base, with a space remaining between these layers. The semiconductor layers are covered with a thin dielectric, which partially limits a flow of current, and the space is filled. During a subsequent heat treatment, dopants diffuse out of the conductive material into the epitaxial semiconductor layer, where they form a doping region. The thin dielectric limits the diffusion of the dopants into the semiconductor substrate and prevents the propagation of crystal lattice defects into the epitaxial semiconductor layer.

摘要翻译： 为了制造垂直晶体管，设置沟槽，其沟槽由单晶形式的半导体衬底形成，其基底由多晶半导体衬底形成。 过渡区域设置在侧壁和底座之间。 沉积半导体层，使得外延半导体层在侧壁上生长并且半导体层在基底上生长，并且在这些层之间保留空间。 半导体层被薄的电介质覆盖，其部分地限制了电流，并且填充了空间。 在随后的热处理期间，掺杂剂从导电材料扩散到外延半导体层中，在其中它们形成掺杂区域。 薄电介质限制掺杂剂到半导体衬底中的扩散，并防止晶格缺陷向外延半导体层的传播。

公开(公告)号：US20060017132A1

公开(公告)日：2006-01-26

申请号：US11167946

申请日：2005-06-28

申请人： Albert Birner ,  Andreas Weber ,  Till Schloesser ,  Joern Luetzen

发明人： Albert Birner ,  Andreas Weber ,  Till Schloesser ,  Joern Luetzen

IPC分类号： H01L29/00

CPC分类号： H01L21/31612 ,  C23C16/345 ,  C23C16/402 ,  C23C16/56 ,  H01L21/02131 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02321 ,  H01L21/02351 ,  H01L21/3141 ,  H01L21/3185

摘要： The present invention relates to a method for producing a dielectric on a semiconductor body having the following steps that are to be performed successively: provision of a semiconductor body, application of a dielectric layer on at least parts of a first surface of the semiconductor body in such a way as at least partly to form an interface between the dielectric layer and the semiconductor body, and thermal annealing of the semiconductor body and the dielectric layer. The method according to the invention is distinguished by the fact that temporally prior to the annealing, for the purpose of improving the saturation and the electrical properties, fluorine-containing particles are introduced into regions of the semiconductor body and/or of the dielectric layer which adjoin the interface. The present invention furthermore relates to a corresponding semiconductor structure.

摘要翻译： 本发明涉及一种在半导体本体上制造电介质的方法，其具有以下步骤：连续进行：提供半导体本体，在半导体本体的第一表面的至少一部分上施加电介质层 这种方式至少部分地形成介电层和半导体本体之间的界面，以及半导体本体和电介质层的热退火。 根据本发明的方法的区别在于，在退火之前的时间上，为了提高饱和度和电性能，将含氟颗粒引入到半导体本体和/或电介质层的区域中，其中 毗邻接口。 本发明还涉及相应的半导体结构。

公开(公告)号：US06861312B2

公开(公告)日：2005-03-01

申请号：US10233969

申请日：2002-09-03

申请人： Albert Birner ,  Matthias Goldbach ,  Joern Luetzen

发明人： Albert Birner ,  Matthias Goldbach ,  Joern Luetzen

IPC分类号： H01L21/334 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8242

CPC分类号： H01L21/76232 ,  H01L21/763 ,  H01L27/1087 ,  H01L29/66181

摘要： An insulation region, for example, an oxide collar, is formed in a trench structure for a DRAM by first widening a first trench region of the trench that is to be formed, in particular, a base region thereof. At least part of the widened region is then provided with a material region for the insulation region.

摘要翻译： 通过首先加宽待形成的沟槽的第一沟槽区域，特别是其基极区域，形成用于DRAM的沟槽结构中的绝缘区域，例如氧化物环。 然后至少部分加宽区域设置有用于绝缘区域的材料区域。