公开(公告)号：US07521346B2

公开(公告)日：2009-04-21

申请号：US11875524

申请日：2007-10-19

申请人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

IPC分类号： H01L21/4763

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US20080245658A1

公开(公告)日：2008-10-09

申请号：US12141476

申请日：2008-06-18

申请人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

发明人： Alessandro C. Callegari ,  Martin M. Frank ,  Rajarao Jammy ,  Dianne L. Lacey ,  Fenton R. McFeely ,  Sufi Zafar

IPC分类号： C23C14/00

CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6659

摘要： A compound metal comprising HfSiN which is a n-type metal having a workfunction of about 4.0 to about 4.5, preferably about 4.3, eV which is thermally stable on a gate stack comprising a high k dielectric and an interfacial layer. Furthermore, after annealing the stack of HfSiN/high k dielectric/ interfacial layer at a high temperature (on the order of about 1000° C.), there is a reduction of the interfacial layer, thus the gate stack produces a very small equivalent oxide thickness (12 Å classical), which cannot be achieved using TaSiN.

摘要翻译： 包含HfSiN的复合金属，其是具有约4.0至约4.5，优选约4.3的功函数的n型金属，其在包含高k电介质和界面层的栅极堆叠上是热稳定的。 此外，在高温（约1000℃）左右的HfSiN /高k电介质/界面层的堆叠退火之后，界面层的减少，因此栅叠层产生非常小的等效氧化物 厚度（经典），不能用TaSiN实现。

公开(公告)号：US20080017936A1

公开(公告)日：2008-01-24

申请号：US11477707

申请日：2006-06-29

申请人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

发明人： Douglas A. Buchanan ,  Eduard A. Cartier ,  Kevin K. Chan ,  Leland Chang ,  Christopher P. D'Emic ,  Martin M. Frank ,  Evgeni Gusev ,  Jin-Ping Han ,  Rajarao Jammy ,  Vamsi K. Paruchuri ,  Sufi Zafar

IPC分类号： H01L29/94 ,  H01L29/76 ,  H01L31/00

CPC分类号： H01L21/823857 ,  H01L21/28167 ,  H01L21/28194 ,  H01L29/51 ,  H01L29/513 ,  H01L29/78

摘要： A semiconductor structure, particularly a gate stack, useful in field effect transistors (FETs) in which the threshold voltage thereof is controlled by introducing a fixed spatial distribution of electric charge density to the gate dielectric material and a method of forming the same are provided. nFETs and/or pFETs structures are disclosed. In accordance with the present invention, the fixed spatial distribution of electric charge density of the gate stack or FET denotes an electrical charge density that occupies space which remains substantially constant as a function of time under device operation conditions and is non-zero at least at one location within the dielectric material or at its interface with the channel, gate electrode, spacer, or any other structural elements of the device.

摘要翻译： 提供了一种半导体结构，特别是栅极堆叠，其中通过向栅极电介质材料引入电荷密度的固定空间分布来控制其阈值电压的场效应晶体管（FET）及其形成方法。 公开了nFET和/或pFET结构。 根据本发明，栅极堆叠或FET的电荷密度的固定空间分布表示占空间的电荷密度，其在器件操作条件下作为时间的函数保持基本上恒定，并且至少在 电介质材料内的一个位置，或其与沟道，栅电极，间隔物或器件的任何其它结构元件的界面。

公开(公告)号：US08193051B2

公开(公告)日：2012-06-05

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US20090152642A1

公开(公告)日：2009-06-18

申请号：US12355368

申请日：2009-01-16

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L27/092 ,  H01L21/336 ,  H01L21/02

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07452767B2

公开(公告)日：2008-11-18

申请号：US11500254

申请日：2006-08-07

申请人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, Jr. ,  Cyril Cabral, Jr. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： A method of forming a CMOS structure, and the device produced therefrom, having improved threshold voltage and flatband voltage stability. The inventive method includes the steps of providing a semiconductor substrate having an nFET region and a pFET region; forming a dielectric stack atop the semiconductor substrate comprising an insulating interlayer atop a high k dielectric; removing the insulating interlayer from the nFET region without removing the insulating interlayer from the pFET region; and providing at least one gate stack in the pFET region and at least one gate stack in the nFET region. The insulating interlayer can be AlN or AlOxNy. The high k dielectric can be HfO2, hafnium silicate or hafnium silicon oxynitride. The insulating interlayer can be removed from the nFET region by a wet etch including a HCl/H2O2 peroxide solution.

摘要翻译： 一种形成CMOS结构的方法及其制造的器件，具有改进的阈值电压和平带电压稳定性。 本发明的方法包括提供具有nFET区和pFET区的半导体衬底的步骤; 在所述半导体衬底上形成包括在高k电介质顶上的绝缘夹层的电介质叠层; 从nFET区域去除绝缘中间层而不从pFET区域去除绝缘中间层; 以及在pFET区域中提供至少一个栅极堆叠以及在nFET区域中提供至少一个栅极堆叠。 绝缘中间层可以是AlN或AlO x N y Y。 高k电介质可以是HfO 2，硅酸铪或铪硅氮氧化物。 可以通过包含HCl / H 2 O 2 O 2过氧化物溶液的湿蚀刻从nFET区域去除绝缘中间层。

公开(公告)号：US20080182389A1

公开(公告)日：2008-07-31

申请号：US12062972

申请日：2008-04-04

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

IPC分类号： H01L21/479

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.

摘要翻译： 一种半导体结构，特别是pFET，其包括介电常数大于SiO 2的介电常数和大于50％的Ge或Si含量的至少一种其它装置， 提供材料堆栈工程的阈值/平带电压调谐。 本发明中考虑的其它方法包括例如在用于电荷固定的电介质的顶部和/或通过形成工程化的沟道区域之间使用绝缘夹层。 本发明还涉及一种制造这种CMOS结构的方法。

公开(公告)号：US20080142894A1

公开(公告)日：2008-06-19

申请号：US12040350

申请日：2008-02-29

申请人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

发明人： Philippe M. Vereecken ,  Veeraraghavan S. Basker ,  Cyril Cabral ,  Emanuel I. Cooper ,  Hariklia Deligianni ,  Martin M. Frank ,  Rajarao Jammy ,  Vamsi Krishna Paruchuri ,  Katherine L. Saenger ,  Xiaoyan Shao

IPC分类号： H01L27/088 ,  H01L29/423

CPC分类号： H01L21/2885 ,  C25D3/50 ,  C25D5/02 ,  C25D5/024 ,  C25D5/54 ,  C25D7/123 ,  C25D9/04 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/28114 ,  H01L21/76885 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78648

摘要： A method is provided for electroplating a gate metal or other conducting or semiconducting material directly on a dielectric such as a gate dielectric. The method involves selecting a substrate, dielectric layer, and electrolyte solution or melt, wherein the combination of the substrate, dielectric layer, and electrolyte solution or melt allow an electrochemical current to be passed from the substrate through the dielectric layer into the electrolyte solution or melt. Methods are also provided for electrochemical modification of dielectrics utilizing through-dielectric current flow.

摘要翻译： 提供了一种用于将栅极金属或其它导电或半导体材料直接电镀在诸如栅极电介质的电介质上的方法。 该方法包括选择衬底，电介质层和电解质溶液或熔体，其中衬底，电介质层和电解质溶液或熔体的组合允许电化学电流从衬底通过电介质层进入电解质溶液或 熔化。 还提供了利用电介质电流流动的电介质电化学修饰方法。

公开(公告)号：US20110165767A1

公开(公告)日：2011-07-07

申请号：US13047172

申请日：2011-03-14

申请人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Nestor A. Bojarczuk, JR. ,  Cyril Cabral, JR. ,  Eduard A. Cartier ,  Matthew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Supratik Guha ,  Rajarao Jammy ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/28

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

摘要： The present invention provides a semiconductor structure including a semiconductor substrate having a plurality of source and drain diffusion regions located therein, each pair of source and drain diffusion regions are separated by a device channel. The structure further includes a first gate stack of pFET device located on top of some of the device channels, the first gate stack including a high-k gate dielectric, an insulating interlayer abutting the gate dielectric and a fully silicided metal gate electrode abutting the insulating interlayer, the insulating interlayer includes an insulating metal nitride that stabilizes threshold voltage and flatband voltage of the p-FET device to a targeted value and is one of aluminum oxynitride, boron nitride, boron oxynitride, gallium nitride, gallium oxynitride, indium nitride and indium oxynitride. A second gate stack of an nFET devices is located on top remaining device channels, the second gate stack including a high-k gate dielectric and a fully silicided gate electrode located directly atop the high-k gate dielectric.

摘要翻译： 本发明提供一种半导体结构，其包括具有位于其中的多个源极和漏极扩散区域的半导体衬底，每对源极和漏极扩散区域由器件沟道分离。 该结构还包括位于一些器件通道顶部的pFET器件的第一栅极堆叠，第一栅极堆叠包括高k栅极电介质，邻接栅极电介质的绝缘夹层和邻接绝缘体的完全硅化金属栅电极 中间层，绝缘中间层包括将p-FET器件的阈值电压和扁平带电压稳定到目标值的绝缘金属氮化物，并且是氮氧化铝，氮化硼，氮氧化硼，氮化镓，氮氧化镓，氮化铟和铟中的一种 氮氧化物。 nFET器件的第二栅极堆叠位于顶部剩余器件沟道上，第二栅极堆叠包括高k栅极电介质和直接位于高k栅极电介质顶部的完全硅化栅电极。

公开(公告)号：US07655994B2

公开(公告)日：2010-02-02

申请号：US11259644

申请日：2005-10-26

申请人： Eduard A. Cartier ,  Mathew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

发明人： Eduard A. Cartier ,  Mathew W. Copel ,  Martin M. Frank ,  Evgeni P. Gousev ,  Paul C. Jamison ,  Rajarao Jammy ,  Barry P. Linder ,  Vijay Narayanan

IPC分类号： H01L29/94 ,  H01L21/326

CPC分类号： H01L29/513 ,  H01L21/28194 ,  H01L21/28238 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor structure, particularly a pFET, which includes a dielectric material that has a dielectric constant of greater than that of SiO2 and a Ge or Si content of greater than 50% and at least one other means for threshold/flatband voltage tuning by material stack engineering is provided. The other means contemplated in the present invention include, for example, utilizing an insulating interlayer atop the dielectric for charge fixing and/or by forming an engineered channel region. The present invention also relates to a method of fabricating such a CMOS structure.