公开(公告)号：US06540591B1

公开(公告)日：2003-04-01

申请号：US09837606

申请日：2001-04-18

申请人： Alexander J. Pasadyn ,  Christopher H. Raeder ,  Anthony J. Toprac

发明人： Alexander J. Pasadyn ,  Christopher H. Raeder ,  Anthony J. Toprac

IPC分类号： B24B100

CPC分类号： B24B37/013 ,  B24B21/10 ,  B24B37/042 ,  B24B49/04

摘要： A method for polishing wafers includes providing a wafer having a process layer formed thereon; providing a polishing tool having a plurality of control zones and being adapted to polish the process layer based on an operating recipe, the operating recipe having a control variable corresponding to each of the control zones; measuring a pre-polish thickness profile of the process layer; comparing the pre-polish thickness profile to a target thickness profile to determine a desired removal profile; determining values for the control variables associated with the control zones based on the desired removal profile; and modifying the operating recipe of the polishing tool based on the values determined for the control variables. A processing line includes a polishing tool, a metrology tool, and a process controller. The polishing tool is adapted to polish a wafer having a process layer formed thereon based on an operating recipe. The polishing tool includes a plurality of control zones and the operating recipe includes a control variable corresponding to each of the control zones. The metrology tool is adapted to measure a pre-polish thickness profile of the process layer. The process controller is adapted to compare the pre-polish thickness profile to a target thickness profile to determine a desired removal profile, determine values for the control variables associated with the control zones based on the desired removal profile, and modify the operating recipe of the polishing tool based on the values determined for the control variables.

摘要翻译： 抛光晶片的方法包括提供其上形成有工艺层的晶片; 提供具有多个控制区域并且适于基于操作配方抛光所述处理层的抛光工具，所述操作配方具有对应于每个所述控制区域的控制变量; 测量处理层的预抛光厚度轮廓; 将预抛光厚度轮廓与目标厚度轮廓进行比较以确定期望的移除轮廓; 基于期望的移除轮廓来确定与控制区域相关联的控制变量的值; 并且基于为控制变量确定的值来修改抛光工具的操作配方。 处理线包括抛光工具，计量工具和过程控制器。 抛光工具适于基于操作配方抛光其上形成有工艺层的晶片。 抛光工具包括多个控制区，操作配方包括对应于每个控制区的控制变量。 测量工具适用于测量工艺层的预抛光厚度轮廓。 过程控制器适于将预抛光厚度分布与目标厚度分布进行比较以确定期望的去除曲线，基于期望的去除曲线来确定与控制区域相关联的控制变量的值，并修改其中的操作配方 基于为控制变量确定的值的抛光工具。

公开(公告)号：US07307002B2

公开(公告)日：2007-12-11

申请号：US11099339

申请日：2005-04-04

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

IPC分类号： H01L21/76

CPC分类号： H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

摘要翻译： 公开了一种用于在半导体晶片中定义多晶硅层的方法。 使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。 使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

公开(公告)号：US06379216B1

公开(公告)日：2002-04-30

申请号：US09427463

申请日：1999-10-22

申请人： Christopher H. Raeder

发明人： Christopher H. Raeder

IPC分类号： B24B4900

CPC分类号： B24B37/11 ,  B24B21/14 ,  B24D9/085

摘要： A rotary chemical-mechanical polishing apparatus with multiple fluid-bearing platens for use in semiconductor fabrication is described together with a method for chemical-mechanical polishing of semiconductor substrates (“wafers”). A single polishing pad is affixed to a pad backing composed of a thin metal membrane. A polishing fluid is introduced onto an upper surface of the polishing pad. One or more wafers are held face down upon the upper surface of the polishing pad by carriers. Fluid-bearing platens are placed below a lower surface of the pad backing and located directly underneath each wafer. While polishing wafers, the polishing pad and pad backing are rotated about their common center, each carrier and wafer pair is rotated about its common center, the carriers apply a down force on the wafers, and the fluid-bearing platens support the pad backing. The fluid-bearing platens support the pad backing with a fluid flow that exerts a pressure on the pad backing. Within a single fluid-bearing platen, multiple zones of different fluid flow rates allow control of the polishing uniformity. Further, the fluid flow rate distribution of each fluid-bearing platen can be individually controlled.

摘要翻译： 与半导体基板（“晶片”）的化学机械抛光方法一起描述具有用于半导体制造的多个流体轴承压板的旋转化学机械抛光装置。 单个抛光垫固定到由薄金属膜构成的衬垫背衬上。 抛光液被引入抛光垫的上表面。 一个或多个晶片通过载体正面朝下地保持在抛光垫的上表面上。 流体轴承压板放置在垫背面的下表面下方，并位于每个晶片的正下方。 抛光晶片时，抛光垫和衬垫背部围绕其公共中心旋转，每个载体和晶片对围绕其公共中心旋转，载体在晶片上施加向下的力，并且流体承载压板支撑垫衬垫。 流体支承压板用垫片衬垫上施加压力的流体流支撑衬垫背衬。 在单个流体承载压板内，不同流体流速的多个区域允许控制抛光均匀性。 此外，可以单独地控制每个流体轴承压板的流体流量分布。

公开(公告)号：US06444564B1

公开(公告)日：2002-09-03

申请号：US09198121

申请日：1998-11-23

申请人： Christopher H. Raeder

发明人： Christopher H. Raeder

IPC分类号： H01L214763

CPC分类号： H01L21/76819 ,  H01L21/76837

摘要： A method is presented for forming a liner upon spaced interconnect structures arranged upon a semiconductor topography. An oxide layer may be deposited to form the liner. The spaced interconnect structures may each include an interlevel dielectric portion arranged upon a metal interconnect portion, with gaps defined between adjacent interconnect structures. A low k dielectric material may be deposited over the interconnect structures such that the low k material substantially fills the gaps between adjacent interconnect structures. The low k dielectric material may then be planarized, preferably by chemical mechanical polishing.

摘要翻译： 提出了一种在半导体形貌上布置的隔开的互连结构上形成衬垫的方法。 可以沉积氧化物层以形成衬垫。 间隔开的互连结构可以各自包括布置在金属互连部分上的层间电介质部分，在相邻互连结构之间限定间隙。 低k介电材料可以沉积在互连结构上，使得低k材料基本上填充相邻互连结构之间的间隙。 然后，可以优选通过化学机械抛光来将低k电介质材料平坦化。

公开(公告)号：US06284622B1

公开(公告)日：2001-09-04

申请号：US09426208

申请日：1999-10-25

申请人： William J. Campbell ,  H. Jim Fulford ,  Christopher H. Raeder ,  Craig W. Christian ,  Thomas Sonderman

发明人： William J. Campbell ,  H. Jim Fulford ,  Christopher H. Raeder ,  Craig W. Christian ,  Thomas Sonderman

IPC分类号： H01L2176

CPC分类号： H01L22/20 ,  H01L21/76229

摘要： A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

摘要翻译： 提供了一种用于填充沟槽的方法。 提供了至少形成有第一层的晶片。 在第一层中形成沟槽。 测量沟槽的深度。 基于沟槽的深度确定目标厚度。 在沟槽上形成第二层目标厚度。 处理线包括沟槽蚀刻工具，第一计量工具，沟槽填充工具和自动过程控制器。 沟槽蚀刻工具适于在晶片上的第一层中形成沟槽。 第一个计量工具适用于测量沟槽的深度。 沟槽填充工具适于基于操作配方在第一层上形成第二层。 自动过程控制器适于基于沟槽的深度确定目标厚度，并且基于目标厚度修改沟槽填充工具的操作配方。

公开(公告)号：US07008301B1

公开(公告)日：2006-03-07

申请号：US09383876

申请日：1999-08-26

申请人： Christopher H. Raeder

发明人： Christopher H. Raeder

IPC分类号： B24B1/00

CPC分类号： B24B37/042 ,  B24B41/005 ,  B24B53/017

摘要： According to an example embodiment, the present invention is directed to a CMP apparatus having a polishing table, a wafer carrier adapted to carry a wafer on a pad, and a conditioning wheel. If the pad is being polished in a center-fast or center-slow manner, the conditioning wheel is used to condition the pad and to improve the center-fast or center-slow condition. Benefits of using this embodiment include improved wafer quality, improved pad life, a reduction in defective wafers, and faster production.

摘要翻译： 根据示例性实施例，本发明涉及一种具有抛光台，适于将晶片载于衬垫上的晶片载体和调节轮的CMP设备。 如果衬垫以中心或中心缓慢的方式抛光，则调节轮用于调节衬垫并改善中心快速或中心缓慢的状态。 使用该实施例的优点包括提高晶片质量，改善焊盘寿命，减少缺陷晶片以及更快地生产。

公开(公告)号：US06454899B1

公开(公告)日：2002-09-24

申请号：US09885455

申请日：2001-06-19

申请人： William J. Campbell ,  H. Jim Fulford ,  Christopher H. Raeder ,  Craig W. Christian ,  Thomas Sonderman

发明人： William J. Campbell ,  H. Jim Fulford ,  Christopher H. Raeder ,  Craig W. Christian ,  Thomas Sonderman

IPC分类号： H01L2100

CPC分类号： H01L22/20 ,  H01L21/76229

摘要： A method for filling a trench is provided. A wafer having at least a first layer formed thereon is provided. A trench is formed in the first layer. The depth of the trench is measured. A target thickness is determined based on the depth of the trench. A second layer of the target thickness is formed over the trench. A processing line includes a trench etch tool, a first metrology tool, a trench fill tool, and an automatic process controller. The trench etch tool is adapted to form a trench in a first layer on a wafer. The first metrology tool is adapted to measure the depth of the trench. The trench fill tool is adapted to form a second layer over the first layer based on an operating recipe. An automatic process controller is adapted to determine a target thickness based on the depth of the trench and modify the operating recipe of the trench fill tool based on the target thickness.

摘要翻译： 提供了一种用于填充沟槽的方法。 提供了至少形成有第一层的晶片。 在第一层中形成沟槽。 测量沟槽的深度。 基于沟槽的深度确定目标厚度。 在沟槽上形成第二层目标厚度。 处理线包括沟槽蚀刻工具，第一计量工具，沟槽填充工具和自动过程控制器。 沟槽蚀刻工具适于在晶片上的第一层中形成沟槽。 第一个计量工具适用于测量沟槽的深度。 沟槽填充工具适于基于操作配方在第一层上形成第二层。 自动过程控制器适于基于沟槽的深度确定目标厚度，并且基于目标厚度修改沟槽填充工具的操作配方。

公开(公告)号：US6155915A

公开(公告)日：2000-12-05

申请号：US275654

申请日：1999-03-24

申请人： Christopher H. Raeder

发明人： Christopher H. Raeder

IPC分类号： B24B21/06 ,  B24B37/04 ,  B24B29/00 ,  B24B5/00

CPC分类号： B24B37/04 ,  B24B21/06

摘要： A polishing assembly for CMP of semiconductors includes an air bearing platen having multiple concentric rings of air holes, with each ring defining an air delivery zone. Each ring includes air source holes alternating with air drain holes. A distribution plate is mated with the platen, and the distribution plate has alternating rings of air supply and air exhaust rings. The air supply rings include air supply apertures that are aligned with the air source holes in the platen, and the air exhaust rings include air exhaust apertures that are aligned with the air drain holes in the platen. With this structure, the air distribution profile of each air delivery zone can be established relatively independently of the profiles of the other zones.

摘要翻译： 用于半导体CMP的抛光组件包括具有多个气孔同心环的空气轴承压板，每个环限定空气输送区。 每个环包括与排气孔交替的空气源孔。 分配板与压板配合，分配板具有交替的供气环和排气环。 空气供给环包括与压板中的空气源孔对准的空气供给孔，排气环包括与压板中的排气孔对准的排气孔。 利用这种结构，可以相对独立于其它区域的轮廓来建立每个空气输送区域的空气分配轮廓。

公开(公告)号：US6106661A

公开(公告)日：2000-08-22

申请号：US74892

申请日：1998-05-08

申请人： Christopher H. Raeder ,  Kevin D. Shipley ,  Peter A. Burke

发明人： Christopher H. Raeder ,  Kevin D. Shipley ,  Peter A. Burke

IPC分类号： B24B37/26 ,  B24D13/14 ,  C23F1/02

CPC分类号： B24B37/26

摘要： A polishing pad having a wear level indicator and a polishing system employing the same is provided. A polishing pad, in accordance with one embodiment of the invention, includes a pad structure and an indicator, disposed in the pad structure, indicating the wear level of the pad structure. The pad structure may, for example, include a top pad and a bottom pad with the indicator being disposed in the top pad. The wear level may, for example, be a critical thickness of the polishing pad which indicates the end of the pad lifetime or which indicates the need to change polishing processing. The use of a wear level indicator allows for efficient and reliable pad wear level indication.

摘要翻译： 提供了一种具有磨损水平指示器和使用其的抛光系统的抛光垫。 根据本发明的一个实施例的抛光垫包括设置在垫结构中的衬垫结构和指示器，指示衬垫结构的磨损水平。 垫结构可以例如包括顶垫和底垫，其中指示器设置在顶垫中。 磨损水平可以例如是抛光垫的临界厚度，其指示焊盘寿命的结束或者指示需要改变抛光处理。 使用磨损水平指示器可以实现高效可靠的垫磨损水平指示。

公开(公告)号：US07888269B2

公开(公告)日：2011-02-15

申请号：US11256184

申请日：2005-10-24

申请人： Kouros Ghandehari ,  Hirokazu Tokuno ,  David Matsumoto ,  Christopher H. Raeder ,  Christopher Foster ,  Weidong Qian ,  Minh Van Ngo

发明人： Kouros Ghandehari ,  Hirokazu Tokuno ,  David Matsumoto ,  Christopher H. Raeder ,  Christopher Foster ,  Weidong Qian ,  Minh Van Ngo

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： G03F7/091 ,  H01L21/0276

摘要： A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over the layer of SiON, SiRN or Si3N4 and forming a second layer of anti-reflective material over the first layer. The method also includes using the first layer, second layer and layer of SiON, SiRN or Si3N4 as a mask when etching a pattern in the layer of semiconducting material.

摘要翻译： 一种方法包括在半导体材料层上形成氮氧化硅（SiON），富硅氮化物（SiRN）或氮化硅（Si3N4）层。 该方法还包括在SiON，SiRN或Si 3 N 4层上形成第一层抗反射材料，并在第一层上形成第二层抗反射材料。 该方法还包括当蚀刻半导体材料层中的图案时，使用第一层，第二层和SiON，SiRN或Si3N4层作为掩模。