公开(公告)号：US07307002B2

公开(公告)日：2007-12-11

申请号：US11099339

申请日：2005-04-04

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher H. Raeder ,  Christopher M. Foster ,  Harpreet Kaur Sachar ,  Kashmir Singh Sahota

IPC分类号： H01L21/76

CPC分类号： H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

摘要翻译： 公开了一种用于在半导体晶片中定义多晶硅层的方法。 使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。 使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

公开(公告)号：US20060223278A1

公开(公告)日：2006-10-05

申请号：US11099339

申请日：2005-04-04

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher Raeder ,  Christopher Foster ,  Harpreet Sachar ,  Kashmir Sahota

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun ,  Krishnashree Achuthan ,  Christopher Raeder ,  Christopher Foster ,  Harpreet Sachar ,  Kashmir Sahota

IPC分类号： H01L21/76

CPC分类号： H01L27/105 ,  H01L21/3212 ,  H01L21/32139 ,  H01L21/76229 ,  H01L27/1052 ,  H01L27/11526 ,  H01L27/11543 ,  H01L27/11568

摘要： A method is disclosed for the definition of the poly-1 layer in a semiconductor wafer. A non-critical mask is used to recess field oxides in the periphery prior to poly-1 deposition by an amount equal to the final poly-1 thickness. A complimentary non-critical mask is used to permit CMP of the core to expose the tops of core oxide mesas from the shallow isolation trenches.

摘要翻译： 公开了一种用于在半导体晶片中定义多晶硅层的方法。 使用非临界掩模在聚-1沉积之前将外围的场氧化物凹入等于最终聚-1厚度的量。 使用互补的非关键掩模来允许芯的CMP将浅层隔离沟的核心氧化物台面的顶部暴露出来。

公开(公告)号：US07078314B1

公开(公告)日：2006-07-18

申请号：US10407999

申请日：2003-04-03

申请人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun

发明人： Unsoon Kim ,  Hiroyuki Kinoshita ,  Yu Sun

IPC分类号： H01L21/76

CPC分类号： H01L21/76229 ,  H01L27/105 ,  H01L27/1052

摘要： The present invention discloses a memory device having an improved periphery isolation region and core isolation region. A first trench is formed in a core region. Substrate material bordering the first trench is then oxidized to form a first liner. The first liner is then removed. A second trench is then formed in a periphery region. A second oxidation is then performed such that a second liner is formed from the substrate material bordering the first and second trenches. A dielectric trench fill having substantially uniform density is then deposited in the first and second trenches.

摘要翻译： 本发明公开了一种具有改进的外围隔离区域和核心隔离区域的存储器件。 第一沟槽形成在芯区域中。 然后与第一沟槽接壤的衬底材料被氧化以形成第一衬里。 然后将第一个衬垫取出。 然后在周边区域中形成第二沟槽。 然后执行第二氧化，使得第二衬垫由与第一和第二沟槽接壤的衬底材料形成。 然后在第一和第二沟槽中沉积具有基本均匀密度的电介质沟槽填料。

公开(公告)号：US07439141B2

公开(公告)日：2008-10-21

申请号：US10277395

申请日：2002-10-22

申请人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

发明人： Unsoon Kim ,  Yu Sun ,  Hiroyuki Kinoshita ,  Kuo-Tung Chang ,  Harpreet K. Sachar ,  Mark S. Chang

IPC分类号： H01L21/00

CPC分类号： H01L21/76235

摘要： A method for performing shallow trench isolation during semiconductor fabrication that improves trench corner rounding is disclosed. The method includes etching trenches into a silicon substrate between active regions, and performing a double liner oxidation process on the trenches. The method further includes performing a double sacrificial oxidation process on the active regions, wherein corners of the trenches are substantially rounded by the four oxidation processes.

摘要翻译： 公开了一种用于在半导体制造期间进行浅沟槽隔离的方法，其改善沟槽角圆化。 该方法包括将沟槽蚀刻到有源区域之间的硅衬底中，并在沟槽上执行双衬层氧化工艺。 该方法还包括对活性区域进行双重牺牲氧化处理，其中沟槽的角通过四个氧化过程基本上被圆化。

公开(公告)号：US06995437B1

公开(公告)日：2006-02-07

申请号：US10869774

申请日：2004-06-16

申请人： Hiroyuki Kinoshita ,  Yu Sun ,  Basab Banerjee ,  Christopher M. Foster ,  John R. Behnke ,  Cyrus Tabery

发明人： Hiroyuki Kinoshita ,  Yu Sun ,  Basab Banerjee ,  Christopher M. Foster ,  John R. Behnke ,  Cyrus Tabery

IPC分类号： H01L31/119

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

摘要翻译： 一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。 衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。 第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。 此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。 该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。 此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

公开(公告)号：US06780708B1

公开(公告)日：2004-08-24

申请号：US10382744

申请日：2003-03-05

申请人： Hiroyuki Kinoshita ,  Yu Sun ,  Basab Banerjee ,  Christopher M. Foster ,  John R. Behnke ,  Cyrus Tabery

发明人： Hiroyuki Kinoshita ,  Yu Sun ,  Basab Banerjee ,  Christopher M. Foster ,  John R. Behnke ,  Cyrus Tabery

IPC分类号： H01L218242

CPC分类号： H01L27/105 ,  H01L27/11568 ,  H01L27/11573

摘要： A method for forming a semiconductor device that includes a line and space pattern with variable pitch and critical dimensions in a layer on a substrate. The substrate includes a first region (e.g., a core region) and a second region (e.g., a periphery region). A first sub-line and space pattern in the first region comprises a space of a dimension (A) less than achievable by lithographic processes alone. Further, a second sub-line and space pattern in the second region comprises at least one line including a second critical dimension (B) achievable by lithography. The method uses two critical masking steps to form a hard mask that includes in the core region a critical dimension (A) less than achievable at a resolution limit of lithography. Further, the method uses a single etch step to transfer the pattern of the hard mask to the layer.

摘要翻译： 一种用于形成半导体器件的方法，其包括在衬底上的层中具有可变节距和临界尺寸的线和间隔图案。 衬底包括第一区域（例如芯区域）和第二区域（例如，周边区域）。 第一区域中的第一子线和空间图案包括尺寸（A）的空间小于单独通过光刻工艺可实现的尺寸。 此外，第二区域中的第二子线和空间图案包括至少一条线，其包括通过光刻可实现的第二临界尺寸（B）。 该方法使用两个关键的掩模步骤来形成硬掩模，其在芯部区域中包括小于在光刻的分辨率极限下可实现的临界尺寸（A）。 此外，该方法使用单个蚀刻步骤将硬掩模的图案转移到该层。

公开(公告)号：US06444530B1

公开(公告)日：2002-09-03

申请号：US09318429

申请日：1999-05-25

申请人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

发明人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

IPC分类号： H01L21336

CPC分类号： H01L27/11521 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/115 ,  H01L2924/0002 ,  Y10T428/12542 ,  Y10T428/1259 ,  Y10T428/12625 ,  Y10T428/12778 ,  H01L2924/00

摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

摘要翻译： 在闪速存储器件中形成触点的方法利用局部互连处理技术。 局部互连处理技术允许接触件与存储器单元相关联的堆叠栅极对接或重叠。 接触可以包括钨。 堆叠的栅极被也覆盖绝缘间隔物的阻挡层覆盖。

公开(公告)号：US5907781A

公开(公告)日：1999-05-25

申请号：US49517

申请日：1998-03-27

申请人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

发明人： Hung-Sheng Chen ,  Unsoon Kim ,  Yu Sun ,  Chi Chang ,  Mark Ramsbey ,  Mark Randolph ,  Tatsuya Kajita ,  Angela Hui ,  Fei Wang ,  Mark Chang

IPC分类号： H01L21/60 ,  H01L21/768 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/335

CPC分类号： H01L21/76897 ,  H01L21/76895

摘要： A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

公开(公告)号：US06040597A

公开(公告)日：2000-03-21

申请号：US23166

申请日：1998-02-13

申请人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

发明人： Unsoon Kim ,  Yowjuang W. Liu ,  Yu Sun

IPC分类号： H01L21/762 ,  H01L29/788

CPC分类号： H01L21/76232 ,  H01L21/76237

摘要： A wet etching process for establishing isolation grooves in a flash memory core wafer includes depositing nitride and/or oxide layers on a silicon substrate of the wafer, depositing a photoresist layer thereon, and then exposing predetermined portions of the photoresist layer to ultraviolet light to establish a desired groove pattern in the photoresist layer. A dry etching process is then used to remove the nitride and/or oxide layers beneath the groove pattern of the photoresist layer to thereby expose portions of the substrate. Next, the wafer is disposed in a wet etching solution such as potassium hydroxide to form grooves in the exposed portions of the silicon substrate. The wafer is oriented and disposed in the bath as appropriate for forming V-shaped grooves, such that after etching, the angled walls of the grooves can be easily exposed to a dopant beam directly above the wafer, without having to tilt the wafer or beam source. Thereby, the walls of the grooves are easily implanted with dopant.

摘要翻译： 用于在闪速存储器芯晶片中建立隔离槽的湿蚀刻工艺包括在晶片的硅衬底上沉积氮化物和/或氧化物层，在其上沉积光致抗蚀剂层，然后将光致抗蚀剂层的预定部分暴露于紫外光以建立 在光致抗蚀剂层中的期望的凹槽图案。 然后使用干蚀刻工艺去除光致抗蚀剂层的凹槽图案下方的氮化物和/或氧化物层，从而暴露衬底的部分。 接下来，将晶片设置在诸如氢氧化钾的湿蚀刻溶液中，以在硅衬底的暴露部分中形成凹槽。 晶片被定向并适当地设置在浴中以形成V形槽，使得在蚀刻之后，槽的成角度的壁可以容易地暴露于直接在晶片上方的掺杂剂束，而不必使晶片或光束倾斜 资源。 因此，槽的壁容易用掺杂剂注入。

公开(公告)号：US06004862A

公开(公告)日：1999-12-21

申请号：US8320

申请日：1998-01-20

申请人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

发明人： Unsoon Kim ,  Hung-Sheng Chen ,  Kashmir Sahota ,  Yu Sun

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76202 ,  H01L21/76224

摘要： A process for forming a semiconductor integrated circuit with a core area densely populated with active devices and with a periphery area less densely populated with active devices as compared to the core area, comprising the steps of: forming a first layer of first insulator material above a semiconductor substrate having a core area and a periphery area, wherein the first insulator material constitutes a polish stop for polishing processes and also as an oxidation barrier; patterning the first layer of first insulator material to expose first portions of the semiconductor substrate substantially only in the core area while using the first insulator material to substantially mask the periphery area; forming a plurality of trenches into the exposed first portions of semiconductor substrate in the core area; filling the plurality of trenches with an insulator; polishing down to the first layer of first insulator material; removing the first layer of first insulator material; forming a second layer of first insulator material over the core and periphery areas; forming openings down into the second layer of first insulator material to expose second portions of the semiconductor substrate substantially only in the periphery area while using the second layer to substantially mask the core area; and forming an isolation region in the exposed second portions of the semiconductor substrate.

摘要翻译： 一种用于形成半导体集成电路的方法，所述半导体集成电路具有密集地填充有有源器件的核心区域，并且与所述核心区域相比具有较少密集地填充有源器件的外围区域，包括以下步骤：在第一绝缘体材料的上方形成第一层 具有芯区域和周边区域的半导体衬底，其中所述第一绝缘体材料构成用于抛光工艺的抛光止挡件以及氧化屏障; 图案化第一绝缘体材料层，以在使用第一绝缘体材料基本上遮蔽周边区域的同时，在半导体衬底的基本上仅在芯部区域露出第一部分; 在芯区域中的半导体衬底的暴露的第一部分中形成多个沟槽; 用绝缘体填充多个沟槽; 抛光到第一绝缘体材料层; 去除第一绝缘体材料的第一层; 在所述芯和外围区域上形成第二绝缘体材料层; 将第一绝缘体材料的第二层向下形成开口，以便在使用第二层基本上掩蔽核心区域时，基本上只在周边区域露出半导体衬底的第二部分; 以及在半导体衬底的暴露的第二部分中形成隔离区。