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    Self-aligned polysilicon polish
    3.
    发明授权
    Self-aligned polysilicon polish 有权
    自对准多晶硅抛光

    公开(公告)号：US06610577B1

    公开(公告)日：2003-08-26

    申请号：US10150204

    申请日：2002-05-15

    申请人： Jack F. Thomas ,  Unsoon Kim ,  Krishnashree Achuthan

    发明人： Jack F. Thomas ,  Unsoon Kim ,  Krishnashree Achuthan

    IPC分类号： H01L218247

    CPC分类号： H01L27/11526 ,  H01L21/28273 ,  H01L21/3212 ,  H01L27/11521 ,  H01L27/11531 ,  H01L29/66825

    摘要： A method for removing polysilicon from isolation regions on a substrate during semiconductor fabrication is disclosed. The method includes depositing a layer of polysilicon over the substrate, and depositing at least one dielectric layer over the polysilicon. The method further includes polishing the polysilicon from the isolation regions, wherein the dielectric layers act as a polishing stop, resulting in regions of polysilicon that are self-aligned to the trench isolation regions.

    摘要翻译： 公开了一种用于在半导体制造期间从衬底上的隔离区域去除多晶硅的方法。 该方法包括在衬底上沉积多晶硅层，以及在多晶硅上沉积至少一个电介质层。 该方法还包括从隔离区域抛光多晶硅，其中介电层用作抛光停止，从而产生与沟槽隔离区自对准的多晶硅区域。

    Method for controlling poly 1 thickness and uniformity in a memory array fabrication process
    4.
    发明授权
    Method for controlling poly 1 thickness and uniformity in a memory array fabrication process 有权
    用于控制存储器阵列制造工艺中聚1厚度和均匀性的方法

    公开(公告)号：US07294573B1

    公开(公告)日：2007-11-13

    申请号：US11035188

    申请日：2005-01-13

    申请人： Krishnashree Achuthan ,  Unsoon Kim ,  Kashmir Sahota ,  Patriz C. Regalado

    发明人： Krishnashree Achuthan ,  Unsoon Kim ,  Kashmir Sahota ,  Patriz C. Regalado

    IPC分类号： H01L21/302 ,  H01L21/461

    CPC分类号： H01L21/7684

    摘要： According to one exemplary embodiment, a method includes planarizing a layer of polysilicon situated over field oxide regions on a substrate to form polysilicon segments, where the polysilicon segments have top surfaces that are substantially planar with top surfaces of the field oxide regions, and where the field oxide regions have a first height and the polysilicon segments have a first thickness. The method further includes removing a hard mask over a peripheral region of the substrate. According to this exemplary embodiment, the method further includes etching the polysilicon segments to cause the polysilicon segments to have a second thickness, which causes the top surfaces of the polysilicon segments to be situated below the top surfaces of the field oxide regions. The polysilicon segments can be etched by using a wet etch process. The polysilicon segments are situated in a core region of the substrate.

    摘要翻译： 根据一个示例性实施例，一种方法包括将位于衬底上的场氧化物区域上的多晶硅层平坦化以形成多晶硅段，其中多晶硅段具有与场氧化物区域的顶表面基本上平面的顶表面， 场氧化物区域具有第一高度，并且多晶硅段具有第一厚度。 该方法还包括在衬底的周边区域上去除硬掩模。 根据该示例性实施例，该方法还包括蚀刻多晶硅段以使多晶硅段具有第二厚度，这导致多晶硅段的顶表面位于场氧化物区的顶表面之下。 可以通过使用湿蚀刻工艺来蚀刻多晶硅段。 多晶硅段位于衬底的芯区域中。

    Hard mask removal process including isolation dielectric refill
    5.
    发明授权
    Hard mask removal process including isolation dielectric refill 有权
    硬掩模去除工艺包括隔离介质再填充

    公开(公告)号：US06607925B1

    公开(公告)日：2003-08-19

    申请号：US10165837

    申请日：2002-06-06

    申请人： Unsoon Kim ,  Dawn M. Hopper ,  Yider Wu ,  Krishnashree Achuthan

    发明人： Unsoon Kim ,  Dawn M. Hopper ,  Yider Wu ,  Krishnashree Achuthan

    IPC分类号： H01L2100

    CPC分类号： H01L21/76224 ,  H01L21/0337 ,  H01L21/31116 ,  H01L21/32139

    摘要： A method for repairing an isolation dielectric damaged during a semiconductor fabrication process is disclosed in which a hard mask material is used to pattern a first material, the first material having openings therein exposing isolation regions comprising a first isolation dielectric layer. The method includes etching the hard mask material from the first material, wherein the etch creates gouges in the first isolation dielectric layer, and depositing a second layer of isolation dielectric over the first material, wherein the second isolation dielectric layer fills the gouges in the first isolation dielectric layer. The method further includes polishing on the second layer of isolation dielectric to remove the second layer of isolation dielectric from the first material.

    摘要翻译： 公开了一种用于修复在半导体制造工艺期间损坏的隔离电介质的方法，其中使用硬掩模材料来图案化第一材料，其中在其中具有开口的第一材料暴露出包括第一隔离介电层的隔离区域。 该方法包括从第一材料蚀刻硬掩模材料，其中蚀刻在第一隔离电介质层中产生沟槽，以及在第一材料上沉积第二隔离电介质层，其中第二隔离电介质层填充第一隔离电介质层中的沟槽 隔离介电层。 该方法还包括在第二层隔离电介质上抛光以从第一材料去除第二隔离电介质层。

    Method for semiconductor wafer planarization by CMP stop layer formation
    8.
    发明授权
    Method for semiconductor wafer planarization by CMP stop layer formation 失效
    通过CMP停止层形成的半导体晶片平面化方法

    公开(公告)号：US06770523B1

    公开(公告)日：2004-08-03

    申请号：US10190397

    申请日：2002-07-02

    申请人： Kashmir S. Sahota ,  Jeffrey P. Erhardt ,  Arvind Halliyal ,  Minh Van Ngo ,  Krishnashree Achuthan

    发明人： Kashmir S. Sahota ,  Jeffrey P. Erhardt ,  Arvind Halliyal ,  Minh Van Ngo ,  Krishnashree Achuthan

    IPC分类号： H01L218238

    CPC分类号： H01L21/76229 ,  H01L21/31053

    摘要： A method of manufacturing an integrated circuit is provided having a semiconductor wafer. A chemical-mechanical polishing stop layer is deposited on the semiconductor wafer and a first photoresist layer is processed over the chemical-mechanical polishing stop layer. The chemical-mechanical polishing stop layer and the semiconductor wafer are patterned to form a shallow trench and a shallow trench isolation material is deposited on the chemical-mechanical polishing stop layer and in the shallow trench. A second photoresist layer is processed over the shallow trench isolation material leaving the shallow trench uncovered. The uncovered shallow trench is then treated to become a chemical-mechanical polishing stop area. The shallow trench isolation material is then chemical-mechanical polished to be co-planar with the chemical-mechanical stop layer and the chemical-mechanical polishing stop treated area.

    摘要翻译： 提供了具有半导体晶片的集成电路的制造方法。 化学机械抛光停止层沉积在半导体晶片上，并且在化学机械抛光停止层上处理第一光致抗蚀剂层。 化学机械抛光停止层和半导体晶片被图案化以形成浅沟槽，浅沟槽隔离材料沉积在化学机械抛光停止层和浅沟槽中。 在浅沟槽隔离材料上处理第二光致抗蚀剂层，留下未覆盖的浅沟槽。 然后将未覆盖的浅沟槽处理成为化学机械抛光停止区域。 然后将浅沟槽隔离材料进行化学机械抛光以与化学 - 机械停止层和化学 - 机械抛光停止处理区共面。

    Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure
    9.
    发明授权
    Tin palladium activation with maximized nuclei density and uniformity on barrier material in interconnect structure 有权
    锡钯活化，在互连结构中的阻挡材料上具有最大的核密度和均匀性

    公开(公告)号：US06472310B1

    公开(公告)日：2002-10-29

    申请号：US10118511

    申请日：2002-04-08

    申请人： Krishnashree Achuthan ,  Sergey Lopatin

    发明人： Krishnashree Achuthan ,  Sergey Lopatin

    IPC分类号： H01L214763

    CPC分类号： H01L21/76843 ,  H01L21/288 ,  H01L21/76873 ,  H01L2221/1089 ,  Y10S977/701 ,  Y10S977/712 ,  Y10S977/721

    摘要： For fabricating an interconnect structure formed within an interconnect opening surrounded by dielectric material, a layer of diffusion barrier material is formed on at least one wall of the interconnect opening. An activation layer comprised of palladium is formed on the layer of diffusion barrier material when the interconnect opening is immersed in an activation bath comprised of tin ions and palladium ions. The tin ions have a tin ion concentration in the activation bath that is greater than a palladium ion concentration in the activation bath. A layer of seed material is deposited on the activation layer in an electroless deposition process, and the interconnect opening is filled with a conductive fill material grown from the layer of seed material. A layer of silicon rich material may be formed on the layer of diffusion barrier material before deposition of the activation layer such that the activation layer is formed on the layer of silicon rich material. In that case, a ratio of the tin ion concentration to the palladium ion concentration in the activation bath is adjusted to decrease with an amount of silicon atoms of the layer of silicon rich material deposited on the layer of diffusion barrier material. The present invention may be practiced to particular advantage when the layer of seed material and the conductive fill material are comprised of copper.

    摘要翻译： 为了制造形成在由电介质材料包围的互连开口内的互连结构，在互连开口的至少一个壁上形成扩散阻挡材料层。 当互连开口浸入由锡离子和钯离子组成的活化浴中时，在扩散阻挡材料层上形成由钯构成的活化层。 锡离子在活化浴中的锡离子浓度大于活化浴中的钯离子浓度。 一种种子材料在无电沉积工艺中沉积在活化层上，并且互连开口填充有从种子材料层生长的导电填充材料。 可以在沉积激活层之前在扩散阻挡材料层上形成富硅材料层，使得活化层形成在富硅材料层上。 在这种情况下，调节活化浴中锡离子浓度与钯离子浓度的比例，随着沉积在扩散阻挡材料层上的富硅材料层的硅原子量而减小。 当种子材料层和导电填充材料由铜组成时，本发明可以特别有利。

    Security Layer and Methods for Protecting Tenant Data in a Cloud-Mediated Computing Network
    10.
    发明申请
    Security Layer and Methods for Protecting Tenant Data in a Cloud-Mediated Computing Network 有权
    用于保护云计算网络中的租户数据的安全层和方法

    公开(公告)号：US20140075568A1

    公开(公告)日：2014-03-13

    申请号：US13606979

    申请日：2012-09-07

    申请人： Shiju Sathyadevan ,  P. Venkat Rangan ,  Krishnashree Achuthan

    发明人： Shiju Sathyadevan ,  P. Venkat Rangan ,  Krishnashree Achuthan

    IPC分类号： G06F21/24

    CPC分类号： G06F21/6218 ,  G06F21/554

    摘要： A system for protecting data managed in a cloud-computing network from malicious data operations includes an Internet-connected server and software executing on the server from a non-transitory physical medium, the software providing a first function for generating one or more security tokens that validate one or more computing operations to be performed on the data, a second function for generating a hash for each token generated, the hash detailing, in a secure fashion, the operation type or types permitted by the one or more tokens, a third function for brokering two-party signature of the one or more tokens, and a fourth function for dynamically activating the one or more signed tokens for a specific time window required to perform the operations permitted by the token.

    摘要翻译： 用于保护在云计算网络中管理的数据免受恶意数据操作的系统包括互联网连接的服务器和从非暂时物理介质在服务器上执行的软件，该软件提供用于生成一个或多个安全令牌的第一功能， 验证要对数据执行的一个或多个计算操作，用于为所生成的每个令牌生成散列的第二功能，以安全的方式，所述一个或多个令牌允许的操作类型或类型的散列细节，第三功能 用于代理一个或多个令牌的两方签名，以及用于在执行令牌所允许的操作所需的特定时间窗口中动态激活一个或多个签名令牌的第四功能。