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    Method and apparatus for flexible and programmable clock crossing control with dynamic compensation
    2.
    发明授权
    Method and apparatus for flexible and programmable clock crossing control with dynamic compensation 有权
    用于灵活可编程时钟交叉控制与动态补偿的方法和装置

    公开(公告)号：US07269754B2

    公开(公告)日：2007-09-11

    申请号：US10335418

    申请日：2002-12-30

    申请人： Sridhar Ramaswamy ,  Amit Bodas ,  Zohar B. Bogin ,  David E. Freker ,  Suryaprasad R. Kareenahalli

    发明人： Sridhar Ramaswamy ,  Amit Bodas ,  Zohar B. Bogin ,  David E. Freker ,  Suryaprasad R. Kareenahalli

    IPC分类号： G06F1/02

    CPC分类号： G06F5/06 ,  G11C7/22 ,  G11C7/222

    摘要： A system and method for crossing clocks from a source clock to a destination clock is disclosed. In one embodiment, a source clock phase enable signal is used to enable a set of latch components to selectively input a source clock pulse. The outputs of the latch components may be selected by a multiplexor according to the phases of the destination clock. In another embodiment, a time delay may be passed into the destination clock domain and may be calculated by a number of destination clock cycle time periods. In certain circumstances, the time delay may be adjusted to compensate for longer delays in the clock crossing process.

    摘要翻译： 公开了一种从源时钟到目的地时钟的时钟交叉的系统和方法。 在一个实施例中，源时钟相位使能信号用于使得一组锁存器组件能够选择性地输入源时钟脉冲。 锁存器组件的输出可以由多路复用器根据目的时钟的相位来选择。 在另一个实施例中，可以将时间延迟传递到目的时钟域，并且可以通过多个目的地时钟周期时间周期来计算。 在某些情况下，可以调整时间延迟以补偿时钟跨越处理中的更长的延迟。

    Cross chip transfer mechanism for a memory repeater chip in a Dram memory system
    3.
    发明授权
    Cross chip transfer mechanism for a memory repeater chip in a Dram memory system 有权
    用于内存中继器芯片的交叉芯片传输机制

    公开(公告)号：US06564335B1

    公开(公告)日：2003-05-13

    申请号：US09540318

    申请日：2000-03-31

    申请人： David E. Freker

    发明人： David E. Freker

    IPC分类号： G06F104

    CPC分类号： G06F13/1689 ,  G06F13/4059

    摘要： According to one embodiment, a method of transferring data across a semiconductor chip comprises transmitting data from a first Rambus asic cell to a second Rambus asic cell using clock pulses generated at a first clock generator and sampling the data at the second Rambus asic cell using clock pulses generated at a second clock generator.

    摘要翻译： 根据一个实施例，一种在半导体芯片上传送数据的方法包括使用在第一时钟发生器处产生的时钟脉冲将数据从第一Rambus asic单元发送到第二Rambus asic单元，并使用时钟对第二Rambus asic单元进行数据采样 在第二时钟发生器产生的脉冲。

    Method and apparatus for detecting time domains on a communication channel
    4.
    发明授权
    Method and apparatus for detecting time domains on a communication channel 失效
    用于检测通信信道上的时域的方法和装置

    公开(公告)号：US06408398B1

    公开(公告)日：2002-06-18

    申请号：US09474338

    申请日：1999-12-29

    申请人： David E. Freker ,  Andrew M. Volk

    发明人： David E. Freker ,  Andrew M. Volk

    IPC分类号： G06F104

    CPC分类号： G06F13/4027

    摘要： According to one embodiment, a computer system is disclosed. The computer system includes a memory controller, a first Rambus channel coupled to the memory controller, a memory system coupled to the first Rambus channel and a second Rambus channel coupled to the memory system. The memory system is adaptable to determine the number of time domains on the first Rambus channel and the second Rambus channel. In a further embodiment, the memory system is adaptable to levelize memory devices coupled to the first and second Rambus channels.

    摘要翻译： 根据一个实施例，公开了一种计算机系统。 计算机系统包括存储器控制器，耦合到存储器控制器的第一Rambus通道，耦合到第一Rambus通道的存储器系统和耦合到存储器系统的第二Rambus通道。 存储器系统适用于确定第一Rambus通道和第二Rambus通道上的时域数量。 在另一个实施例中，存储器系统适于对与第一和第二Rambus通道耦合的存储器件进行调平。

    Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state
    5.
    发明授权
    Method and apparatus for dynamically placing portions of a memory in a reduced power consumtion state 失效
    用于在降低的功耗状态下动态地放置存储器的部分的方法和装置

    公开(公告)号：US5835435A

    公开(公告)日：1998-11-10

    申请号：US982876

    申请日：1997-12-02

    申请人： Zohar Bogin ,  David E. Freker

    发明人： Zohar Bogin ,  David E. Freker

    IPC分类号： G11C5/14 ,  G11C7/22 ,  G11C8/12 ,  G11C11/4076 ,  G11C8/00

    CPC分类号： G11C11/4076 ,  G11C5/14 ,  G11C7/22 ,  G11C8/12

    摘要： An apparatus and method for dynamically placing portions of a memory in a reduced power consumption state. Requests to access a memory that includes a plurality of rows of memory components are received. One or more of the plurality of rows of memory components are placed in a reduced power consumption state based on the requests while one or more other rows of the plurality of rows are accessed.

    摘要翻译： 一种用于在降低的功耗状态下动态地放置存储器的部分的装置和方法。 接收到访问包括多行存储器组件的存储器的请求。 所述多行存储器组件中的一个或多个在所述多个行中的一个或多个其他行被访问的同时，基于所述请求被置于降低的功耗状态。

    Optimizing page size in mixed memory array using address multiplexing
    8.
    发明授权
    Optimizing page size in mixed memory array using address multiplexing 有权
    使用地址复用优化混合内存阵列中的页面大小

    公开(公告)号：US6041016A

    公开(公告)日：2000-03-21

    申请号：US205509

    申请日：1998-12-04

    申请人： David E. Freker

    发明人： David E. Freker

    IPC分类号： G11C8/12 ,  G11C8/14 ,  G11C8/00

    CPC分类号： G11C8/12 ,  G11C8/14

    摘要： The present invention is a method and apparatus for addressing a memory array. The memory array has N rows of memory devices with different page sizes. A memory address corresponding to one of the N rows of memory devices is generated. A device bank address is selected corresponding to a device size and a device page size of the one of the N rows of memory devices.

    摘要翻译： 本发明是用于寻址存储器阵列的方法和装置。 存储器阵列具有N行具有不同页面大小的存储器件。 产生对应于N行存储器件之一的存储器地址。 对应于N行存储器件的设备大小和设备页面大小来选择设备库地址。

    Pre-decode conditional command generation for reduced SDRAM cycle latency
    9.
    发明授权
    Pre-decode conditional command generation for reduced SDRAM cycle latency 失效
    预解码条件命令生成以减少SDRAM周期延迟

    公开(公告)号：US06442645B1

    公开(公告)日：2002-08-27

    申请号：US09205447

    申请日：1998-12-04

    申请人： David E. Freker

    发明人： David E. Freker

    IPC分类号： G06F1200

    CPC分类号： G06F13/161 ,  G06F12/0215

    摘要： A method and apparatus for reducing the latency of a cycle initiated by a bus-mastering agent to a memory array is described. The method and corresponding apparatus involves partially decoding a current memory cycle to generate intermediate signals and providing one or more “safe” indicator signals indicating the status of a previous memory cycle. A circuit receives the intermediate signals and the one or more safe indicator signals, and determines whether it is safe to issue a chip select to the memory array, notwithstanding the fact that the command to be issued to the memory array is not yet known. If the cycle is a page-hit, then no further commands or chip select signals are required for the balance of the memory cycle. If the cycle is a row-miss or page-miss, further chip select assertions are required and the responsibility to assert the chip select signal is transferred from the device to a finite state machine.

    摘要翻译： 描述了一种用于将由总线控制代理发起的周期的等待时间减少到存储器阵列的方法和装置。 所述方法和相应的装置涉及对当前存储器周期进行部分解码以产生中间信号并提供指示先前存储器周期的状态的一个或多个“安全”指示符信号。 电路接收中间信号和一个或多个安全指示符信号，并且确定是否安全地向存储器阵列发出芯片选择，尽管事实上要发布到存储器阵列的命令尚不知道。 如果循环是页命中的，则对于存储器周期的平衡，不需要进一步的命令或芯片选择信号。 如果循环是行错或页错，则需要进一步的芯片选择断言，并且断言片选信号的责任从器件转移到有限状态机。

    Method and apparatus providing fast access to a shared resource on a computer bus
    10.
    发明授权
    Method and apparatus providing fast access to a shared resource on a computer bus 失效
    提供对计算机总线上的共享资源的快速访问的方法和装置

    公开(公告)号：US5678009A

    公开(公告)日：1997-10-14

    申请号：US599921

    申请日：1996-02-12

    申请人： Kuljit S. Bains ,  Kenneth M. Crocker ,  David E. Freker

    发明人： Kuljit S. Bains ,  Kenneth M. Crocker ,  David E. Freker

    IPC分类号： G06F13/18 ,  G06F12/00 ,  G06F13/16 ,  G06T1/60 ,  G09G5/00 ,  G09G5/39 ,  G06F13/38

    CPC分类号： G06F13/161

    摘要： A method and apparatus for transferring control of a memory bus, providing access to a memory array, from a controller having control of the memory bus to a controller desiring control of the memory bus are described. The method requires generating an access request directed to the controller having control from the controller desiring control, which is then detected by the controller desiring control. A determination is made as to whether the memory bus is being used, by the controller having control, by sampling the row address strobe (#RAS) line. A fast bus transfer sequence is initiated if the memory bus is not in use, the fast transfer sequence transferring control of the memory bus to the controller desiring control after a first time period. Alternatively, a slow bus transfer sequence is initiated, when the memory bus use is over, if the memory bus is in use. The slow transfer sequence transfers control to the controller desiring control after a second time period, which is longer than the first time period and which includes a precharge period not included in the first time period. Thus when the fast transfer sequence is performed, unnecessary precharging of memory selection circuitry is avoided.

    摘要翻译： 描述了一种用于从具有对存储器总线的控制器的控制器到期望控制存储器总线的控制器传送存储器总线的控制以提供对存储器阵列的访问的方法和装置。 该方法需要从控制器期望控制产生指向具有控制器的控制器的访问请求，然后由控制器期望控制来检测该请求。 通过对行地址选通（#RAS）线进行采样，通过具有控制的控制器来确定存储器总线是否被使用。 如果存储器总线未被使用，则快速总线传送序列被启动，快速传送顺序在第一时间段之后将控制存储器总线传送到控制器。 或者，当存储器总线使用结束时，如果存储器总线正在使用，则开始缓慢的总线传送序列。 慢转移序列将控制转移到比第一时间段长的第二时间段之后的控制器期望控制，并且包括不包括在第一时间段中的预充电周期。 因此，当执行快速传送顺序时，避免了对存储器选择电路的不必要的预充电。