公开(公告)号：US20160118281A1

公开(公告)日：2016-04-28

申请号：US14923828

申请日：2015-10-27

Applicant: Analog Devices, Inc.

Inventor： James Fiorenza

IPC: H01L21/677 ,  H01L21/68

CPC classification number: H01L21/7624 ,  G03F7/00 ,  H01L21/67144 ,  H01L23/525 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/18 ,  H01L2224/24 ,  H01L2224/73267 ,  H01L2224/82 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06593

Abstract: A transfer printing method provides a first wafer having a receiving surface, and removes a second die from a second wafer using a die moving member. Next, the method positions the second die on the receiving surface of the first wafer. Specifically, to position the second die on the receiving surface, the first wafer has alignment structure for at least in part controlling movement of the die moving member.

Abstract translation: 转印技术提供具有接收表面的第一晶片，并且使用模具移动构件从第二晶片移除第二模具。 接下来，该方法将第二管芯定位在第一晶片的接收表面上。 具体地，为了将第二管芯定位在接收表面上，第一晶片具有用于至少部分地控制管芯移动构件的移动的对准结构。

公开(公告)号：US10284194B2

公开(公告)日：2019-05-07

申请号：US14959567

申请日：2015-12-04

Applicant: Analog Devices, Inc.

Inventor： Yogesh Jayaraman Sharma ,  James Fiorenza

IPC: H03K5/22 ,  H03K17/687 ,  H01L27/088 ,  H01L29/20 ,  H03F3/45

Abstract: A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

公开(公告)号：US20160164517A1

公开(公告)日：2016-06-09

申请号：US14959567

申请日：2015-12-04

Applicant: Analog Devices, Inc.

Inventor： Yogesh Jayaraman Sharma ,  James Fiorenza

IPC: H03K17/687 ,  H01L27/088 ,  H01L29/20

CPC classification number: H03K17/6871 ,  H01L27/088 ,  H01L29/2003 ,  H03F3/45188 ,  H03F3/45385 ,  H03F2200/303 ,  H03F2200/75 ,  H03F2203/45036 ,  H03F2203/45182 ,  H03F2203/45184 ,  H03F2203/45188 ,  H03F2203/45202 ,  H03F2203/45208 ,  H03F2203/45224 ,  H03F2203/45656 ,  H03F2203/45674 ,  H03F2203/45676 ,  H03F2203/45701 ,  H03F2203/45702 ,  H03F2203/45722

Abstract: A differential pair gain stage is disclosed. In one embodiment, the gain stage includes a differential pair of depletion-mode transistors, including a first and a second n-type transistor. In certain embodiments of the invention, the depletion mode transistor may be GaN (gallium nitride) field effect transistors. The gain stage includes an active load including one or more depletion mode transistors electrically coupled to at least one of the drains of depletion mode transistors of the differential pair. The active load may include a source follower for maintaining the AC voltages at the drains of the differential pair at a constant value and may further include a casocde stage for setting a fixed drain source voltage across the output transistors to increase the output impedance and gain of the stage.

Abstract translation: 公开了差分对增益级。 在一个实施例中，增益级包括包括第一和第二n型晶体管的耗尽型晶体管的差分对。 在本发明的某些实施例中，耗尽型晶体管可以是GaN（氮化镓）场效应晶体管。 增益级包括有源负载，其包括电耦合到差分对的耗尽型晶体管的至少一个漏极的一个或多个耗尽型晶体管。 有源负载可以包括源极跟随器，用于将差分对的漏极处的AC电压保持在恒定值，并且还可以包括用于在输出晶体管两端设置固定的漏极源电压的casocde级，以增加输出阻抗和增益 舞台。

公开(公告)号：US10522389B2

公开(公告)日：2019-12-31

申请号：US14923828

申请日：2015-10-27

Applicant: Analog Devices, Inc.

Inventor： James Fiorenza ,  F. Jacob Steigerwald ,  Edward F. Gleason ,  Susan L. Feindt

IPC: G03F7/00 ,  H01L21/762 ,  H01L25/065 ,  H01L25/00 ,  H01L21/67 ,  H01L23/525

Abstract: A transfer printing method provides a first wafer having a receiving surface, and removes a second die from a second wafer using a die moving member. Next, the method positions the second die on the receiving surface of the first wafer. Specifically, to position the second die on the receiving surface, the first wafer has alignment structure for at least in part controlling movement of the die moving member.

公开(公告)号：US20160351666A1

公开(公告)日：2016-12-01

申请号：US15165122

申请日：2016-05-26

Applicant: Analog Devices, Inc.

Inventor： Shrenik Deliwala ,  James Fiorenza ,  Donghyun Jin

IPC: H01L29/15 ,  H01L29/205 ,  H01L21/02 ,  H01L29/20

CPC classification number: H01L29/155 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02686 ,  H01L21/3221 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: A method cold-melts a high conductivity region between a high-resistivity silicon substrate and a gallium-nitride layer to form a trap rich region that substantially immobilizes charge carriers in that region. Such a process should substantially mitigate the parasitic impact of that region on circuits formed at least in part by the gallium-nitride layer.

Abstract translation: 一种方法在高电阻率硅衬底和氮化镓层之间冷熔融高导电率区域，以形成基本上固定该区域中的电荷载流子的富集阱区域。 这种过程应该基本上减轻该区域对至少部分由氮化镓层形成的电路的寄生冲击。

公开(公告)号：US09923060B2

公开(公告)日：2018-03-20

申请号：US15165122

申请日：2016-05-26

Applicant: Analog Devices, Inc.

Inventor： Shrenik Deliwala ,  James Fiorenza ,  Donghyun Jin

IPC: H01L29/20 ,  H01L21/02 ,  H01L21/322 ,  H01L21/324 ,  H01L21/205 ,  H01L21/268 ,  H01L29/15 ,  H01L29/205 ,  H01L29/778

CPC classification number: H01L29/155 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0254 ,  H01L21/02686 ,  H01L21/3221 ,  H01L21/324 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/7787

Abstract: A method cold-melts a high conductivity region between a high-resistivity silicon substrate and a gallium-nitride layer to form a trap rich region that substantially immobilizes charge carriers in that region. Such a process should substantially mitigate the parasitic impact of that region on circuits formed at least in part by the gallium-nitride layer.