公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

申请人： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

发明人： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22

摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US20060107095A1

公开(公告)日：2006-05-18

申请号：US11260987

申请日：2005-10-28

申请人： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

发明人： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

IPC分类号： G06F11/00

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

公开(公告)号：US20060140017A1

公开(公告)日：2006-06-29

申请号：US11100013

申请日：2005-04-06

申请人： Anand Seshadri ,  Jarrod Eliason ,  Sudhir Madan

发明人： Anand Seshadri ,  Jarrod Eliason ,  Sudhir Madan

IPC分类号： G11C11/22 ,  G11C5/14

CPC分类号： G11C11/22

摘要： Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S1) couples the staging capacitance (Cs) to the precharged primary capacitance (130) and then isolates the precharged staging capacitance (Cs) from the primary capacitance (130), and the second switching device (S2, S3) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (130), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.

摘要翻译： 参考发生器系统（108,130）和方法（200）被提供用于为铁电存储器件（102）中的存储器存取操作提供位线参考电压。 参考发生器系统（108,130）包括初级电容（130），对初级电容充电的预充电系统（132）以及具有多个与相应的电压相关联的多个局部参考电路（108a）的参考系统（108） 单独地包括分级电容（Cs）的阵列列，耦合在所述分级电容和所述初级电容（130）之间的第一开关器件（S1）以及耦合在所述分级电容之间的第二开关器件（S 2，S 3） （Cs）和相应阵列列的位线。 第一开关器件（S1）将分级电容（Cs）耦合到预充电的初级电容（130），然后将预充电的分级电容（Cs）与主电容（130）隔离，并且第二开关器件（S2， S 3）将分级电容（Cs）与位线分离，而分级电容Cs耦合到初级电容（130），然后将预充电分级电容（Cs）耦合到位线，以在位线期间向位线提供参考电压 内存访问操作。

公开(公告)号：US07301795B2

公开(公告)日：2007-11-27

申请号：US11260987

申请日：2005-10-28

申请人： John Y. Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Kumar Madan ,  Jarrod Eliason

发明人： John Y. Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Kumar Madan ,  Jarrod Eliason

IPC分类号： G11C11/22

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

公开(公告)号：US07133304B2

公开(公告)日：2006-11-07

申请号：US10805809

申请日：2004-03-22

申请人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  Hugh P. McAdams ,  Anand Seshadri ,  Jarrod Eliason

发明人： Sudhir Kumar Madan ,  Sung-Wei Lin ,  Hugh P. McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US08971138B2

公开(公告)日：2015-03-03

申请号：US13467517

申请日：2012-05-09

申请人： Anand Seshadri ,  Wah Kit Loh

发明人： Anand Seshadri ,  Wah Kit Loh

IPC分类号： G11C29/00 ,  G11C29/50 ,  G11C29/04 ,  G11C29/06 ,  G11C11/41

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5002

摘要： A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

摘要翻译： 一种互补金属氧化物半导体CMOS集成电路的方法，例如包括CMOS静态随机存取存储器（SRAM）单元的集成电路，用于易于经过工作时间的晶体管特性偏移的n沟道晶体管。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，提供静态噪声容限和可写性（Vtrip）屏幕。 CMOS SRAM单元中的每个n沟道晶体管形成在与存储器的外围电路中的p型半导体材料和集成电路中的其它功能隔离的p阱内。 正向和反向体节点偏置电压被施加到待测SRAM单元的隔离p阱，以确定读取干扰或写周期这样的操作是否会在这种偏差下破坏单元。 因此可以识别易受阈值电压偏移的电池。

公开(公告)号：US20130058177A1

公开(公告)日：2013-03-07

申请号：US13467517

申请日：2012-05-09

申请人： Anand Seshadri ,  Wah Kit Loh

发明人： Anand Seshadri ,  Wah Kit Loh

IPC分类号： G11C29/00

CPC分类号： G11C29/50 ,  G11C11/41 ,  G11C29/06 ,  G11C29/50004 ,  G11C29/50016 ,  G11C2029/5002

摘要： A method of screening complementary metal-oxide-semiconductor CMOS integrated circuits, such as integrated circuits including CMOS static random access memory (SRAM) cells, for n-channel transistors susceptible to transistor characteristic shifts over operating time. For the example of SRAM cells formed of cross-coupled CMOS inverters, static noise margin and writeability (Vtrip) screens are provided. Each of the n-channel transistors in the CMOS SRAM cells are formed within p-wells that are isolated from p-type semiconductor material in peripheral circuitry of the memory and other functions in the integrated circuit. Forward and reverse body node bias voltages are applied to the isolated p-wells of the SRAM cells under test to determine whether such operations as read disturb, or write cycles, disrupt the cells under such bias. Cells that are vulnerable to threshold voltage shift over time can thus be identified.

摘要翻译： 一种互补金属氧化物半导体CMOS集成电路的方法，例如包括CMOS静态随机存取存储器（SRAM）单元的集成电路，用于易于经过工作时间的晶体管特性偏移的n沟道晶体管。 对于由交叉耦合CMOS反相器形成的SRAM单元的示例，提供静态噪声容限和可写性（Vtrip）屏幕。 CMOS SRAM单元中的每个n沟道晶体管形成在与存储器的外围电路中的p型半导体材料和集成电路中的其它功能隔离的p阱内。 正向和反向体节点偏置电压被施加到待测SRAM单元的隔离p阱，以确定读取干扰或写周期这样的操作是否会在这种偏差下破坏单元。 因此可以识别易受阈值电压偏移的电池。

公开(公告)号：US08339839B2

公开(公告)日：2012-12-25

申请号：US13363051

申请日：2012-01-31

申请人： Theodore W. Houston ,  Anand Seshadri

发明人： Theodore W. Houston ,  Anand Seshadri

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are floated. A second integrated circuit containing an SRAM cell array, in which each SRAM cell includes a bit-side write passgate, a bit-bar-side read passgate and a bit-bar auxiliary driver transistor. A process of operating the second integrated circuit including a single sided read operation in which source nodes of the auxiliary drivers in both addressed cells and half-addressed cells are biased to a low bias voltage.

摘要翻译： 包含单面写入SRAM单元阵列的第一集成电路，每个SRAM单元具有位通道和辅助位棒驱动晶体管。 包括单向读取操作的第一集成电路的处理，其中寻址单元和半寻址单元中的辅助驱动器的源节点浮动。 包含SRAM单元阵列的第二集成电路，其中每个SRAM单元包括位侧写入通道，位线侧读取通道和位线辅助驱动器晶体管。 包括单向读取操作的第二集成电路的处理，其中寻址单元和半寻址单元中的辅助驱动器的源节点被偏置到低偏置电压。

公开(公告)号：US08301431B2

公开(公告)日：2012-10-30

申请号：US12346036

申请日：2008-12-30

申请人： Keerthinarayan P. Heragu ,  Theodore W. Houston ,  Anand Seshadri ,  Hugh T. Mair

发明人： Keerthinarayan P. Heragu ,  Theodore W. Houston ,  Anand Seshadri ,  Hugh T. Mair

IPC分类号： G06F17/50

CPC分类号： G06F17/5009 ,  G06F2217/10

摘要： A method of accelerating a Monte Carlo (MC) simulation for a system including a first component having a first input parameter and a second component having a second input parameter. The simulation model provided includes a first component model including a first model parameter corresponding to the first input parameter and a second component model having a second model parameter corresponding to the second input parameter. A first acceleration factor for the first component and a second acceleration factor for the second component are calculated based on at least the respective number of instances. A first scaled distribution is computed from the first distribution and a second scaled distribution is computed from the second distribution based on the respective acceleration factors. The MC simulation for the system is run, wherein values for the first model parameter value and second model parameter value are obtained based on the respective scaled distributions.

摘要翻译： 一种加速用于包括具有第一输入参数的第一分量和具有第二输入参数的第二分量的系统的系统的蒙特卡罗（MC）模拟的方法。 提供的模拟模型包括第一分量模型，其包括对应于第一输入参数的第一模型参数和具有对应于第二输入参数的第二模型参数的第二分量模型。 至少基于相应数量的实例来计算第一分量的第一加速因子和第二分量的第二加速因子。 从第一分布计算第一缩放分布，并且基于相应的加速因子从第二分布计算第二缩放分布。 运行系统的MC模拟，其中基于相应的缩放分布获得第一模型参数值和第二模型参数值的值。

公开(公告)号：US08159863B2

公开(公告)日：2012-04-17

申请号：US12782874

申请日：2010-05-19

申请人： Theodore W. Houston ,  Anand Seshadri

发明人： Theodore W. Houston ,  Anand Seshadri

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An SRAM cell containing an auxiliary driver transistor is configured for a single sided write operation. The auxiliary driver transistor may be added to a 5-transistor single-sided-write SRAM cell or to a 7-transistor single-sided-write SRAM cell. The SRAM cell may also include a read buffer. During read operations, the auxiliary drivers are biased. During write operations, the auxiliary drivers in half-addressed SRAM cells are biased and the auxiliary drivers in the addressed SRAM cells may be floated or biased.

摘要翻译： 包含辅助驱动晶体管的SRAM单元被配置用于单面写入操作。 辅助驱动晶体管可以添加到5晶体管单面写入SRAM单元或7晶体管单面写入SRAM单元。 SRAM单元还可以包括读缓冲器。 在读操作期间，辅助驱动器有偏差。 在写操作期间，半寻址SRAM单元中的辅助驱动器偏置，并且寻址的SRAM单元中的辅助驱动器可能浮置或偏置。