公开(公告)号：US20050207201A1

公开(公告)日：2005-09-22

申请号：US10805809

申请日：2004-03-22

申请人： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

发明人： Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams ,  Anand Seshadri ,  Jarrod Eliason

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22

摘要： Methods and ferroelectric devices are presented, in which pulses are selectively applied to ferroelectric memory cell wordlines to discharge cell storage node disturbances while the cell plateline and the associated bitline are held at substantially the same voltage.

摘要翻译： 提出了方法和铁电器件，其中脉冲被选择性地施加到铁电存储器单元字线以放电单元存储节点干扰，同时单元板线和相关联的位线保持在基本上相同的电压。

公开(公告)号：US20060107095A1

公开(公告)日：2006-05-18

申请号：US11260987

申请日：2005-10-28

申请人： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

发明人： John Fong ,  Anand Seshadri ,  Sung-Wei Lin ,  Sudhir Madan ,  Jarrod Eliason

IPC分类号： G06F11/00

CPC分类号： G11C29/50 ,  G11C11/22 ,  G11C2029/5002

摘要： Systems and methods fatigue a ferroelectric memory device. Within a single cycle, a group of selected ferroelectric memory cells is fatigued by reading a first logical value from the cells while also writing a second logical value to the memory cells. The first logical value is temporarily stored into latches of sense amplifiers associated with the selected memory cells in order to decipher logical values. Subsequently, the first logical value is written back to the ferroelectric memory cells and a cycle of the fatigue operation is ended.

摘要翻译： 系统和方法使铁电存储器件疲劳。 在单个周期内，通过从单元读取第一逻辑值，同时向存储单元写入第二逻辑值，使一组选定的铁电存储单元疲劳。 将第一逻辑值临时存储到与所选择的存储器单元相关联的读出放大器的锁存器中，以便解密逻辑值。 随后，将第一逻辑值写回到铁电存储单元，并且结束疲劳操作的循环。

公开(公告)号：US20060140017A1

公开(公告)日：2006-06-29

申请号：US11100013

申请日：2005-04-06

申请人： Anand Seshadri ,  Jarrod Eliason ,  Sudhir Madan

发明人： Anand Seshadri ,  Jarrod Eliason ,  Sudhir Madan

IPC分类号： G11C11/22 ,  G11C5/14

CPC分类号： G11C11/22

摘要： Reference generator systems (108, 130) and methods (200) are presented for providing bitline reference voltages for memory access operations in a ferroelectric memory device (102). The reference generator system (108, 130) comprises a primary capacitance (130), a precharge system (132) that charges the primary capacitance, and a reference system (108) with a plurality of local reference circuits (108a) associated with corresponding array columns that individually comprise a staging capacitance (Cs), a first switching device (S1) coupled between the staging capacitance and the primary capacitance (130), and a second switching device (S2, S3) coupled between the staging capacitance (Cs) and a bitline of the corresponding array column. The first switching device (S1) couples the staging capacitance (Cs) to the precharged primary capacitance (130) and then isolates the precharged staging capacitance (Cs) from the primary capacitance (130), and the second switching device (S2, S3) isolates the staging capacitance (Cs) from the bitline while the staging capacitance Cs is coupled to the primary capacitance (130), and then couples the precharged staging capacitance (Cs) to the bitline to provide a reference voltage to the bitline during the memory access operation.

摘要翻译： 参考发生器系统（108,130）和方法（200）被提供用于为铁电存储器件（102）中的存储器存取操作提供位线参考电压。 参考发生器系统（108,130）包括初级电容（130），对初级电容充电的预充电系统（132）以及具有多个与相应的电压相关联的多个局部参考电路（108a）的参考系统（108） 单独地包括分级电容（Cs）的阵列列，耦合在所述分级电容和所述初级电容（130）之间的第一开关器件（S1）以及耦合在所述分级电容之间的第二开关器件（S 2，S 3） （Cs）和相应阵列列的位线。 第一开关器件（S1）将分级电容（Cs）耦合到预充电的初级电容（130），然后将预充电的分级电容（Cs）与主电容（130）隔离，并且第二开关器件（S2， S 3）将分级电容（Cs）与位线分离，而分级电容Cs耦合到初级电容（130），然后将预充电分级电容（Cs）耦合到位线，以在位线期间向位线提供参考电压 内存访问操作。

公开(公告)号：US20070038805A1

公开(公告)日：2007-02-15

申请号：US11200390

申请日：2005-08-09

申请人： Jarrod Eliason ,  Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams

发明人： Jarrod Eliason ,  Sudhir Madan ,  Sung-Wei Lin ,  Hugh McAdams

IPC分类号： G06F12/00

CPC分类号： G11C29/848 ,  G11C11/22 ,  G11C29/816

摘要： A scheme for dealing with or handling faulty ‘grains’ or portions of a nonvolatile ferroelectric memory array is disclosed. In one example, a grain of the memory is less than a column high and less than a row wide. A replacement operation is performed on the memory portion when a repair programming group finds that an address of the portion corresponds to a failed row address and a failed column address.

摘要翻译： 公开了处理或处理有缺陷的“晶粒”或非易失性铁电存储器阵列的部分的方案。 在一个示例中，存储器的颗粒小于高和小于行宽的列。 当修复编程组发现部分的地址对应于失败的行地址和故障列地址时，对存储器部分执行替换操作。

公开(公告)号：US20070211510A1

公开(公告)日：2007-09-13

申请号：US11409628

申请日：2006-04-24

申请人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

发明人： Sudhir Madan ,  Sung-Wei Lin ,  John Fong

IPC分类号： G11C11/22 ,  G11C5/06 ,  G11C11/42

CPC分类号： G11C11/22 ,  H01L27/11502

摘要： An FeRAM memory array wherein the plate lines run in the direction of word lines is described that provides a reduced plate line resistance in arrays having a common plate line connection. The lower plate line resistance reduces the magnitude of negative spikes on the plate line to reduce the potential for FeCap depolarization. Two or more plate lines of a plurality of columns of memory cells are interconnected along a bit line direction. Some or all of the plate lines of one or more columns of dummy memory cells may also be interconnected to reduce the plate line resistance and minimize any increase in the bit line capacitance for the active cells of the array. The improved FeRAM array provides a reduced data error rate, particularly at fast memory cycle times.

摘要翻译： 描述了其中板线在字线方向上延伸的FeRAM存储器阵列，其在具有公共板线连接的阵列中提供减小的板线电阻。 下板线电阻降低了板线上负尖峰的幅度，以减少FeCap去极化的可能性。 多列存储器单元的两条或多条板条沿位线方向互连。 一个或多个虚拟存储器单元列的一些或全部平板线也可互连，以减小板线电阻并且最小化阵列的有源单元的位线电容的任何增加。 改进的FeRAM阵列提供了降低的数据错误率，特别是在快速的存储周期时间。

公开(公告)号：US20070036012A1

公开(公告)日：2007-02-15

申请号：US11191709

申请日：2005-07-28

申请人： Sudhir Madan ,  Bryan Sheffield

发明人： Sudhir Madan ,  Bryan Sheffield

IPC分类号： G11C7/00

CPC分类号： G11C7/065 ,  G11C11/22

摘要： An amplifier circuit and method is disclosed. The amplifier circuit includes an amplifier section (700), an equalization section (770), and an activation section (720). The P-channel transistors (702, 704) of the amplifier section are coupled to a supply terminal (802). The N-channel transistors (706,708) of the amplifier section are coupled between the P-channel transistors and the first and second input terminals (760, 762), respectively. In the activation section, first and second pull down transistors (722, 724) are coupled between the first and second input terminals, respectively, and a second power supply terminal (726). The control gates of the first and second pull down transistors are coupled to each other. In operation, a voltage signal applied to the first and second input terminals is amplified by the N-channel transistors. A control signal is then applied to couple the first and second input terminals to a supply voltage.

摘要翻译： 公开了放大器电路和方法。 放大器电路包括放大器部分（700），均衡部分（770）和激活部分（720）。 放大器部分的P沟道晶体管（702,704）耦合到电源端子（802）。 放大器部分的N沟道晶体管（706,708）分别耦合在P沟道晶体管和第一和第二输入端（760,762）之间。 在激活部分中，第一和第二下拉晶体管（722,724）分别耦合在第一和第二输入端子与第二电源端子（726）之间。 第一和第二下拉晶体管的控制栅极彼此耦合。 在操作中，施加到第一和第二输入端的电压信号被N沟道晶体管放大。 然后施加控制信号以将第一和第二输入端耦合到电源电压。

公开(公告)号：US20050276089A1

公开(公告)日：2005-12-15

申请号：US10866834

申请日：2004-06-14

申请人： Sudhir Madan ,  John Fong

发明人： Sudhir Madan ,  John Fong

IPC分类号： G11C11/22 ,  G11C17/00

CPC分类号： G11C11/22

摘要： Methods (50, 70) and ferroelectric devices (102) are presented, in which pulses (113) are selectively applied to platelines (PL) of one or more non-selected ferroelectric memory cells (106) during memory access operations to mitigate cell storage node disturbances.

摘要翻译： 提出了方法（50,70）和铁电装置（102），其中脉冲（113）在存储器访问操作期间被选择性地施加到一个或多个未选择的铁电存储器单元（106）的板条（PL），以减轻电池存储 节点干扰。

公开(公告)号：US07463504B2

公开(公告)日：2008-12-09

申请号：US11227936

申请日：2005-09-15

申请人： Sung-Wei Lin ,  Sudhir Madan

发明人： Sung-Wei Lin ,  Sudhir Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22 ,  G11C7/12 ,  G11C7/14

摘要： Methods are described for operating a FeRAM and other such memory devices in a manner that avoids over-voltage breakdown of the gate oxide in memory cells along dummy bit lines used at the edges of memory arrays, the methods comprising floating the dummy bit line during plate line pulsing activity. In one implementation of the present invention the method is applied to a FeRAM dummy cell having a plate line, a dummy bit line, a pass transistor, and a ferroelectric storage capacitor. The method comprises initially grounding the dummy bit line as a preferred pre-condition, however, this step may be considered an optional step if the storage node of the storage capacitor is otherwise grounded. The method then comprises floating the dummy bit line, activating a word line associated with the memory cell, and pulsing the plate line. Alternately, the method comprises applying a positive voltage bias to the dummy bit line in place of, or before floating the dummy bit line. The method may further optionally comprise grounding the dummy bit line after pulsing the plate line, and optionally disabling the word line after grounding the dummy bit line to precondition the cell for the next memory operation.

摘要翻译： 描述了用于以避免在存储器阵列的边缘处沿着虚拟位线的存储器单元中的栅极氧化物的过压击穿的方式来操作FeRAM和其它这样的存储器件的方法，所述方法包括在板期间浮置虚拟位线 线脉冲活动。 在本发明的一个实施方式中，该方法被应用于具有板线，伪位线，传输晶体管和铁电存储电容器的FeRAM虚拟单元。 该方法包括首先将虚拟位线接地作为优选的前提条件，然而，如果存储电容器的存储节点以其他方式接地，则该步骤可以被认为是可选步骤。 该方法然后包括浮置虚拟位线，激活与存储器单元相关联的字线，以及脉冲板线。 或者，该方法包括将代替虚拟位线或浮置虚拟位线之前的正电压偏压施加到虚拟位线。 该方法可以进一步可选地包括在脉冲板线之后对虚拟位线进行接地，并且可选地在使虚拟位线接地之后禁用字线，以对单元进行下一个存储器操作的预处理。

公开(公告)号：US20060081944A1

公开(公告)日：2006-04-20

申请号：US10968798

申请日：2004-10-18

申请人： Sudhir Madan

发明人： Sudhir Madan

IPC分类号： H01L29/76

CPC分类号： G11C11/22 ,  G11C5/063 ,  G11C8/14 ,  H01L27/11502

摘要： A memory circuit and method to reduce array noise due to wordline coupling is disclosed. The circuit includes a plurality of memory cells arranged in rows (702, 704, and 706) and columns (750, 752). Each row has a first part (1102) and a second part (1108). A first conductor (750) is coupled to a respective column of memory cells in each first part. A second conductor (752) is coupled to a respective column in each second part. A third conductor is coupled to a control terminal of each memory cell in the first part (1102) of a first row and the second part (1108) of a second row.

摘要翻译： 公开了一种用于减少由于字线耦合引起的阵列噪声的存储电路和方法。 电路包括排列成行（702,704和706）和列（750,752）的多个存储单元。 每排具有第一部分（1102）和第二部分（1108）。 第一导体（750）耦合到每个第一部分中的存储器单元的相应列。 第二导体（752）在每个第二部分中耦合到相应的列。 第三导体耦合到第一行的第一部分（1102）中的每个存储器单元的控制端子和第二行的第二部分（1108）。

公开(公告)号：US20050146913A1

公开(公告)日：2005-07-07

申请号：US10748041

申请日：2003-12-29

申请人： Sudhir Madan

发明人： Sudhir Madan

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： Ferroelectric memory devices and methods are provided, wherein a cell plateline signal is applied to a ferroelectric target cell capacitor and a zero cancellation capacitor is coupled with a bitline during a memory read operation. A negative pulse is applied to the zero cancellation capacitor during the cell plateline pulse to reduce the voltage on the bitline, thereby facilitating reduced cell plateline voltage levels while still allowing a high percentage of the ferroelectric saturation voltage to be applied across the ferroelectric cell capacitor.

摘要翻译： 提供了铁电存储器件和方法，其中在存储器读取操作期间，将单元板线信号施加到铁电靶电池电容器，并且零消除电容器与位线耦合。 在单元板线脉冲期间，负零脉冲施加到零消除电容器，以降低位线上的电压，从而有助于降低电池板电压电平，同时仍然允许将高百分比的铁电饱和电压施加在铁电单元电容器两端。