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公开(公告)号：US20120032136A1
公开(公告)日：2012-02-09
申请号：US12849864
申请日：2010-08-04
CPC分类号： H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
摘要翻译： 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。
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公开(公告)号：US08994489B2
公开(公告)日：2015-03-31
申请号：US13276523
申请日：2011-10-19
申请人： Andrea Redaelli , Giorgio Servalli
发明人： Andrea Redaelli , Giorgio Servalli
CPC分类号： H01H85/06 , G11C13/0004 , H01H37/32 , H01H85/08 , H01H85/11 , Y10T29/49107
摘要： Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.
摘要翻译： 一些实施例包括具有直接接触导电结构的含钨结构的熔丝。 导电结构可以是含钛结构。 含钨结构和导电结构之间的界面被配置为当通过界面的电流超过预定水平时破裂。 一些实施例包括形成和使用保险丝的方法。 保险丝形成为具有直接接触导电结构的含钨结构。 含钨结构和导电结构之间的界面被配置为当通过界面的电流超过预定水平时破裂。 超过预定水平的电流通过界面破裂界面。
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公开(公告)号：US20100308296A1
公开(公告)日：2010-12-09
申请号：US12481496
申请日：2009-06-09
CPC分类号： H01L45/06 , H01L27/2445 , H01L27/2463 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/1675
摘要： A self-aligned vertical heater element is deposited directly on the silicide of a selection device, and a phase change chalcogenide material is deposited directly on the vertical heater element. The fabrication process allows for self-alignment between the chalcogenide line and vertical heater element. In an embodiment, the vertical heater element is L-shaped, having a vertical wall along the wordline direction and a horizontal base. The vertical wall and the horizontal base may have the same thickness.
摘要翻译： 自对准垂直加热元件直接沉积在选择装置的硅化物上，相变硫族化物材料直接沉积在垂直加热元件上。 制造工艺允许硫族化物管线和垂直加热器元件之间的自对准。 在一个实施例中，垂直加热器元件是L形的，具有沿字线方向的垂直壁和水平底座。 垂直壁和水平底座可以具有相同的厚度。
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公开(公告)号：US08569734B2
公开(公告)日：2013-10-29
申请号：US12849864
申请日：2010-08-04
CPC分类号： H01L45/06 , H01L23/5256 , H01L27/2445 , H01L27/2463 , H01L45/12 , H01L45/1226 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1675 , H01L45/1683
摘要： A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
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公开(公告)号：US20130187120A1
公开(公告)日：2013-07-25
申请号：US13354966
申请日：2012-01-20
CPC分类号： H01L45/124 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.
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公开(公告)号：US20130099888A1
公开(公告)日：2013-04-25
申请号：US13276523
申请日：2011-10-19
申请人： Andrea Redaelli , Giorgio Servalli
发明人： Andrea Redaelli , Giorgio Servalli
CPC分类号： H01H85/06 , G11C13/0004 , H01H37/32 , H01H85/08 , H01H85/11 , Y10T29/49107
摘要： Some embodiments include a fuse having a tungsten-containing structure directly contacting an electrically conductive structure. The electrically conductive structure may be a titanium-containing structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Some embodiments include a method of forming and using a fuse. The fuse is formed to have a tungsten-containing structure directly contacting an electrically conductive structure. An interface between the tungsten-containing structure and the electrically conductive structure is configured to rupture when current through the interface exceeds a predetermined level. Current exceeding the predetermined level is passed through the interface to rupture the interface.
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公开(公告)号：US08962384B2
公开(公告)日：2015-02-24
申请号：US13354966
申请日：2012-01-20
CPC分类号： H01L45/124 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/065 , H01L45/1233 , H01L45/126 , H01L45/1286 , H01L45/142 , H01L45/143 , H01L45/144 , H01L45/148 , H01L45/16
摘要： Memory cells having heaters with angled sidewalls and methods of forming the same are described herein. As an example, a method of forming an array of resistive memory cells can include forming a first resistive memory cell having a first heater element angled with respect to a vertical plane, forming a second resistive memory cell adjacent to the first resistive memory cell and having a second heater element angled with respect to the vertical plane and toward the first heater, and forming a third resistive memory cell adjacent to the first resistive memory cell and having a third heater element angled with respect to the vertical plane and away from the first heater element.
摘要翻译： 具有带有倾斜侧壁的加热器的记忆单元及其形成方法在此描述。 作为示例，形成电阻存储器单元阵列的方法可以包括形成具有相对于垂直平面成角度的第一加热元件的第一电阻式存储单元，形成与第一电阻式存储单元相邻的第二电阻式存储单元，并具有 相对于垂直平面并朝向第一加热器成角度的第二加热器元件，以及形成与第一电阻式存储单元相邻的第三电阻式存储单元，并具有相对于垂直平面成角度且远离第一加热器的第三加热元件 元件。
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8.发明授权Double patterning method for creating a regular array of pillars with dual shallow trench isolation 有权双重图案化方法，用于创建具有双浅沟槽隔离的规则的柱状阵列公开(公告)号：US08921196B2
公开(公告)日：2014-12-30
申请号：US13132602
申请日：2008-12-30
IPC分类号： H01L27/102 , H01L27/24 , H01L21/033 , H01L45/00
CPC分类号： H01L27/2463 , H01L21/0338 , H01L21/76224 , H01L27/1022 , H01L27/2445 , H01L29/0649 , H01L29/41708 , H01L29/42304 , H01L29/66272 , H01L29/732 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144 , H01L45/16
摘要： A method is disclosed for forming vertical bipolar junction transistors including a regular array of base contact pillars and emitter contact pillars with a width below the minimum lithographical resolution F of the lithographic technique employed. In an embodiment, the pillar array features have a dimension of approximately F/2, though this dimension could be reduced down to other values compatible with embodiments of the invention. A storage element, such as a phase change storage element, can be formed above the regular array of base contact pillars and emitter contact pillars.
摘要翻译： 公开了用于形成垂直双极结晶体管的方法，其包括基本接触柱的规则阵列和具有低于所采用的光刻技术的最小光刻分辨率F的宽度的发射极接触柱。 在一个实施例中，柱阵列特征具有大约F / 2的尺寸，尽管该尺寸可以减小到与本发明的实施例相容的其它值。 诸如相变存储元件的存储元件可以形成在基底接触柱和发射极接触柱的规则阵列上方。
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9.发明申请PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE 有权在半导体基板上集成的电子器件中形成差分空间的方法公开(公告)号：US20100047980A1
公开(公告)日：2010-02-25
申请号：US12606997
申请日：2009-10-27
申请人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
发明人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/66553
摘要： A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.
摘要翻译： A在集成在半导体衬底上的电子器件中形成间隔物，其包括：第一和第二晶体管，每个包括从衬底突出的栅电极和相应的源极/漏极区。 该方法包括：在整个电子设备上级联形成第一厚度的第一保护层和第一共形绝缘层; 形成第一掩模以覆盖所述第一晶体管; 去除未被第一掩模覆盖的第一保形绝缘层; 去除第一个面罩; 在整个装置上形成第二厚度的第二共形绝缘层; 并且去除所述绝缘层直到所述保护层暴露以在所述第一晶体管的栅电极的侧壁上形成第一宽度的第一间隔物，并且在所述第二晶体管的栅电极的侧壁上形成第二宽度的第二间隔物 。
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10.发明申请PROCESS FOR FORMING DIFFERENTIAL SPACES IN ELECTRONICS DEVICE INTEGRATED ON A SEMICONDUCTOR SUBSTRATE 审中-公开在半导体基板上集成的电子器件中形成差分空间的方法公开(公告)号：US20080206945A1
公开(公告)日：2008-08-28
申请号：US11680507
申请日：2007-02-28
申请人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
发明人： Giorgio Servalli , Giulio Albini , Carlo Cremonesi
IPC分类号： H01L21/336
CPC分类号： H01L27/105 , H01L27/11526 , H01L27/11546 , H01L29/66553
摘要： A forms spacers in a electronic device integrated on a semiconductor substrate that includes: first and second transistors each comprising a gate electrode projecting from the substrate and respective source/drain regions. The process comprises: forming in cascade a first protective layer and a first conformal insulating layer of a first thickness on the whole electronic device; forming a first mask to cover the first transistor; removing the first conformal insulating layer not covered by the first mask; removing the first mask; forming a second conformal insulating layer of a second thickness on the whole device; and removing the insulating layers until the protective layer is exposed to form first spacers of a first width on the side walls of the gate electrodes of the first transistor and second spacers of a second width on the side walls of the gate electrodes of the second transistor.
摘要翻译： A在集成在半导体衬底上的电子器件中形成间隔物，其包括：第一和第二晶体管，每个包括从衬底突出的栅电极和相应的源极/漏极区。 该方法包括：在整个电子设备上级联形成第一厚度的第一保护层和第一共形绝缘层; 形成第一掩模以覆盖所述第一晶体管; 去除未被第一掩模覆盖的第一保形绝缘层; 去除第一个面罩; 在整个装置上形成第二厚度的第二共形绝缘层; 并且去除所述绝缘层直到所述保护层暴露以在所述第一晶体管的栅电极的侧壁上形成第一宽度的第一间隔物，并且在所述第二晶体管的栅电极的侧壁上形成第二宽度的第二间隔物 。
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