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公开(公告)号：US07010014B1
公开(公告)日：2006-03-07
申请号：US09684528
申请日：2000-10-06
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： The frequency of a skew clock signal is dithered around a base frequency, thereby enabling this clock signal to comply with FCC requirements for electromagnetic emissions within a specified window. Delay is introduced such that the clock signals exhibits slightly different frequencies in successive periods. For example, the frequency of a 100 MHz clock signal can be adjusted to have frequencies of approximately 98, 98.5, 99, 99.5, 100, 100.5, 101, 101.5, and 102 MHz during different periods. Because the frequencies are spread in 0.5 MHz increments, only three frequencies are included in any 1 MHz window. As a result, ⅔ of the energy of the clock signal is not included when determining whether the clock signal meets the FCC electromagnetic emission requirements. By spreading the frequencies above and below the base frequency in a regular manner, the average frequency of the clock signal becomes equal to the base frequency.
摘要翻译： 偏移时钟信号的频率在基频周围抖动，从而使该时钟信号能够符合FCC在指定窗口内对电磁辐射的要求。 引入延迟使得时钟信号在连续的周期中表现出稍微不同的频率。 例如，100MHz时钟信号的频率可以在不同时段期间被调整为具有约98,98.5,99,99.5,100,150.5,101,101.5和102MHz的频率。 由于频率以0.5 MHz为单位进行扩展，所以在1 MHz窗口中只能包含三个频率。 因此，当确定时钟信号是否满足FCC电磁辐射要求时，不包括时钟信号的能量的2/3。 通过以规则的方式扩展基频以上的频率，时钟信号的平均频率等于基频。
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公开(公告)号：US06775342B1
公开(公告)日：2004-08-10
申请号：US09684540
申请日：2000-10-06
IPC分类号： H04L2500
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： After a delay lock loop synchronizes a reference clock signal with a skewed clock signal, a digital phase shifter can be used to shift the skewed clock signal by a small amount with respect to the reference clock signal. The tap/trim settings of a delay line in the main path of the delay lock loop can be transmitted to the digital phase shifter, thereby informing the digital phase shifter of the period of the reference clock signal. In response, the digital phase shifter provides a phase control signal that introduces a delay, which is referenced to the period of the reference clock signal, to either the reference clock signal or the skew clock signal. The phase control signal is proportional to a predetermined fraction of the period of the reference clock signal. The digital phase shifter can be controlled to operate in several modes. In a first fixed mode, the digital phase shifter introduces delay to the skew clock signal. In a second fixed mode, the digital phase shifter introduces delay to the reference clock signal. In a first variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the reference clock signal. In a second variable mode, the digital phase shifter can cause the reference clock signal to lead or lag the skew clock signal by controlling the delay of the skew clock signal.
摘要翻译： 在延迟锁定环路使参考时钟信号与偏斜时钟信号同步之后，数字移相器可用于相对于参考时钟信号将偏斜的时钟信号移位一小段量。 在延迟锁定环路的主路径上的延迟线的抽头/微调设置可被发送到数字移相器，由此通知数字移相器参考时钟信号的周期。 作为响应，数字移相器提供相位控制信号，其将参考时钟信号的周期的延迟引入参考时钟信号或偏斜时钟信号。 相位控制信号与参考时钟信号的周期的预定分数成比例。 数字移相器可以控制在多种模式下工作。 在第一固定模式中，数字移相器将延迟引入到偏斜时钟信号。 在第二固定模式中，数字移相器将延迟引入参考时钟信号。 在第一可变模式中，数字移相器可以通过控制参考时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。 在第二可变模式中，数字移相器可以通过控制偏斜时钟信号的延迟来引起参考时钟信号引导或延迟偏斜时钟信号。
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公开(公告)号：US07187742B1
公开(公告)日：2007-03-06
申请号：US09684529
申请日：2000-10-06
IPC分类号： H03D3/24
CPC分类号： H03L7/07 , G06F1/10 , H03L7/0814
摘要： A digital clock manager is provided. The digital clock manager generates an output clock signal that causes a skewed clock signal to be synchronized with a reference clock signal. Furthermore, the digital clock manager generates a frequency adjusted clock signal that is synchronized with the output clock signal during concurrence periods. The digital clock manager includes a delay lock loop and a digital frequency synthesizer. The delay lock loop generates a synchronizing clock signal that is provided to the digital frequency synthesizer. The output clock signal lags the synchronizing clock signal by a DLL output delay. Similarly, the frequency adjusted clock signal lags the synchronizing clock signal by a DFS output delay. By matching the DLL output delay to the DFS output delay, the digital clock manager synchronizes the output clock signal and the frequency adjusted clock signal.
摘要翻译： 提供数字时钟管理器。 数字时钟管理器产生一个输出时钟信号，使得偏斜的时钟信号与参考时钟信号同步。 此外，数字时钟管理器产生在同步期间与输出时钟信号同步的频率调整时钟信号。 数字时钟管理器包括延迟锁定环和数字频率合成器。 延迟锁定环产生提供给数字频率合成器的同步时钟信号。 输出时钟信号通过DLL输出延迟滞后于同步时钟信号。 类似地，频率调整的时钟信号通过DFS输出延迟滞后于同步时钟信号。 通过将DLL输出延迟与DFS输出延迟相匹配，数字时钟管理器将输出时钟信号和频率调整后的时钟信号同步。
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公开(公告)号：US06289068B1
公开(公告)日：2001-09-11
申请号：US09102740
申请日：1998-06-22
IPC分类号： H03D324
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay for the delay line.
摘要翻译： 延迟锁定环使用具有延迟线的时钟移相器来使参考时钟信号与偏斜时钟信号同步。 延迟线耦合到延迟锁定环的参考输入端，并产生提供给时钟移相器的延迟时钟信号。 时钟移相器从延迟的时钟信号产生一个或多个相移时钟信号。 耦合到延迟线的输出发生器，时钟移相器和延迟锁定环路的输出端子提供延迟时钟信号或相移时钟信号中的一个作为延迟锁定环路的输出时钟信号。 延迟线的传播延迟被设置为使参考时钟信号与延迟锁定环路的反馈输入端上接收到的偏斜时钟信号同步。 相位检测器比较参考时钟信号和偏斜时钟信号，以确定延迟线的适当传播延迟。
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5.发明授权公开(公告)号：US07233532B2
公开(公告)日：2007-06-19
申请号：US10836961
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
发明人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
CPC分类号： H03K19/17776 , H03K19/17744 , H03K19/17752 , H03K19/1776 , H03K19/17764
摘要： Method and apparatus for an interface to a system monitor (1600) is described. A controller (102) accessible via a port interface thereof (110) is configured for read/write access to configuration memory cells (1500) and for read access to status registers (1602). The configuration memory cells (1500) are addressable via a first address space, and the status registers (1602) are addressable via a second address space different from the first address space. The port interface (110) is configured to receive a plurality of signals including a data address signal (124) and a data clock signal (121). The data address signal (124) has address information for accessing either the first address space or the second address space.
摘要翻译： 描述了用于系统监视器（1600）的接口的方法和装置。 经由其端口接口（110）可访问的控制器（102）被配置用于对配置存储器单元（1500）进行读/写访问以及对状态寄存器（1602）的读取访问。 配置存储器单元（1500）可通过第一地址空间寻址，并且状态寄存器（1602）可通过与第一地址空间不同的第二地址空间来寻址。 端口接口（110）被配置为接收包括数据地址信号（124）和数据时钟信号（121）的多个信号。 数据地址信号（124）具有访问第一地址空间或第二地址空间的地址信息。
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公开(公告)号：US06587534B2
公开(公告)日：2003-07-01
申请号：US09892403
申请日：2001-06-26
IPC分类号： H03D324
CPC分类号： H03L7/0814 , G06F1/10 , H03L7/07
摘要： A delay lock loop uses a clock phase shifter with a delay line to synchronize a reference clock signal with a skewed clock signal. The delay line is coupled to a reference input terminal of the delay lock loop and generates a delayed clock signal that is provided to the clock phase shifter. The clock phase shifter generates one or more phase-shifted clock signals from the delayed clock signal. An output generator coupled to the delay line, the clock phase shifter, and an output terminal of the delay lock loop provides either the delayed clock signal or one of the phase-shifted clock signals as an output clock signal of the delayed lock loop. The propagation delay of the delay line is set to synchronize the reference clock signal with the skewed clock signal, which is received on a feedback input terminal of the delay lock loop. A phase detector compares the reference clock signal and the skewed clock signal to determine the appropriate propagation delay.
摘要翻译： 延迟锁定环使用具有延迟线的时钟移相器来使参考时钟信号与偏斜时钟信号同步。 延迟线耦合到延迟锁定环的参考输入端，并产生提供给时钟移相器的延迟时钟信号。 时钟移相器从延迟的时钟信号产生一个或多个相移时钟信号。 耦合到延迟线的输出发生器，时钟移相器和延迟锁定环路的输出端子提供延迟时钟信号或相移时钟信号中的一个作为延迟锁定环路的输出时钟信号。 延迟线的传播延迟被设置为使参考时钟信号与延迟锁定环路的反馈输入端上接收到的偏斜时钟信号同步。 相位检测器比较参考时钟信号和偏斜时钟信号以确定适当的传播延迟。
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公开(公告)号：US07218137B2
公开(公告)日：2007-05-15
申请号：US10837331
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
发明人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
IPC分类号： H03K19/173
CPC分类号： H03K19/17752 , H03K19/17732 , H03K19/17756 , H03K19/1776
摘要： Method and apparatus for dynamic configuration of function block logic of an integrated circuit is described. The integrated circuit includes a reconfiguration port coupled to a controller. The controller is coupled to an array of memory cell. A portion of the array of memory cells is coupled for read/write communication with the controller, and another portion of the array of memory cells is not coupled for read/write communication with the controller. The portion of the array of memory cells is configurable at an operational frequency of the integrated circuit for dynamic reconfiguration of the function block logic of the integrated circuit.
摘要翻译： 描述了用于集成电路的功能块逻辑的动态配置的方法和装置。 集成电路包括耦合到控制器的重配置端口。 控制器耦合到存储器单元的阵列。 存储器单元阵列的一部分被耦合用于与控制器的读/写通信，并且存储器单元阵列的另一部分不耦合用于与控制器的读/写通信。 存储器单元阵列的部分可以在集成电路的工作频率下配置，用于集成电路的功能块逻辑的动态重新配置。
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8.发明授权Reconfiguration port for dynamic reconfiguration—sub-frame access for reconfiguration 有权用于重新配置的动态重新配置 - 子帧访问的重新配置端口公开(公告)号：US07126372B2
公开(公告)日：2006-10-24
申请号：US10836841
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
发明人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
IPC分类号： H03K19/173
CPC分类号： H03K19/173
摘要： Method and apparatus for sub-frame bit access for reconfiguring a logic block of a programmable logic device is described. A reconfiguration port in communication with a controller is provided. The controller is in communication with configuration memory for configuring the logic block. Configuration information is provided via the reconfiguration port. A single data word stored in the configuration memory is read via the controller, modified with the configuration information, and written back into configuration memory. Accordingly, by reading a single data word, in contrast to an entire frame, on-the-fly reconfiguration is facilitated.
摘要翻译： 描述了用于重配置可编程逻辑器件的逻辑块的子帧位访问的方法和装置。 提供了与控制器通信的重新配置端口。 控制器与用于配置逻辑块的配置存储器通信。 配置信息通过重配置端口提供。 通过控制器读取存储在配置存储器中的单个数据字，用配置信息进行修改，并写回到配置存储器中。 因此，通过读取单个数据字，与整个帧相反，便于实时重新配置。
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公开(公告)号：US07109750B2
公开(公告)日：2006-09-19
申请号：US10836960
申请日：2004-04-30
申请人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
发明人： Vasisht Mantra Vadi , David P. Schultz , John D. Logue , John McGrath , Anthony Collins , F. Erich Goetting
IPC分类号： H03K19/173
CPC分类号： H03K19/173
摘要： Method and apparatus for a controller for dynamic configuration is described. The controller comprises a port interface, a read/write interface, and a plurality of flip-flops. The flip-flops, couple the port interface to the read/write interface. The port interface is configured to receive a plurality of signals, where portion of the plurality of signals are pipelined through the plurality of flip-flops responsive to a data clock signal of the plurality of signals. This facilitates reading and writing to storage elements at a rate which is at least approximately a frequency of the data clock signal while operating a device at approximately such frequency in which the controller is instantiated.
摘要翻译： 描述了用于动态配置的控制器的方法和装置。 控制器包括端口接口，读/写接口和多个触发器。 触发器将端口接口耦合到读/写接口。 端口接口被配置为接收多个信号，其中响应于多个信号的数据时钟信号，多个信号的部分通过多个触发器流水线化。 这便于以大约这样的控制器被实例化的频率操作设备的速率，以至少近似于数据时钟信号的频率的速率读取和写入存储元件。
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公开(公告)号：US06445232B1
公开(公告)日：2002-09-03
申请号：US09713707
申请日：2000-11-14
申请人： John D. Logue , F. Erich Goetting
发明人： John D. Logue , F. Erich Goetting
IPC分类号： H03L706
CPC分类号： H03L7/0814 , H03L7/08 , H03L7/083 , H03L7/0991 , H03L7/18 , H03L2207/50
摘要： A digital variable clocking circuit is provided. The variable clocking circuit is configured to receive an input clock signal and to generate an output clock signal having an output clock frequency equal to the frequency of the input clock signal multiplied by a multiplier M and divided by a divisor D. In one embodiment of the present invention, the average frequency of the output clock signal during a concurrence period is equal to the selected frequency because the active edge of the output clock signal is triggered by the rising edge of the reference clock signal during a concurrence. Furthermore, the waveform of the output clock signal is shaped to approximate the waveform of an ideal output clock signal by selectively inserting delays distributed throughout the concurrence period using a Modulo-M delta sigma circuit. The modulo-M delta sigma circuit, which receives modulo value M, a pulse value P, and a clock signal, generates an output signal that includes P pulses spread across M clock periods.
摘要翻译： 提供数字可变时钟电路。 可变时钟电路被配置为接收输入时钟信号并且产生具有等于输入时钟频率的输出时钟频率的输出时钟信号，输出时钟频率等于乘法器M乘以除数D的输入时钟信号的频率。在一个实施例中 本发明在同步期间输出时钟信号的平均频率等于所选择的频率，因为输出时钟信号的有效边沿是在同步期间由参考时钟信号的上升沿触发的。 此外，输出时钟信号的波形通过使用Mod-M delta-sigma电路选择性地插入在整个同步周期内分布的延迟来整形以近似理想输出时钟信号的波形。 接收模数M，脉冲值P和时钟信号的模M-ΔΣ电路产生包括在M个时钟周期内分布的P个脉冲的输出信号。
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