公开(公告)号：US07078785B2

公开(公告)日：2006-07-18

申请号：US10668694

申请日：2003-09-23

申请人： Anthony Ciancio ,  Mark D. Griswold ,  Amudha R. Irudayam ,  Jennifer H. Morrison

发明人： Anthony Ciancio ,  Mark D. Griswold ,  Amudha R. Irudayam ,  Jennifer H. Morrison

IPC分类号： H01L29/00 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L28/75 ,  H01L21/31645 ,  H01L23/5223 ,  H01L28/65 ,  H01L2924/0002 ,  H01L2924/00

摘要： By forming a conductive smoothing layer over the bottom electrode and/or a capacitor dielectric, a MIM capacitor with improved reliability due to reduction of geometrically enhanced electric fields and electrode smoothing is formed. In one embodiment, layer including a refractory metal or a refractory metal-rich nitride, is formed over a first capping layer formed of a refractory nitride. In addition, a second refractory metal or a refractory metal-rich nitride layer may be formed on the capacitor dielectric. The smoothing layer could also be used in other semiconductor devices, such as transistors between a gate electrode and a gate dielectric.

摘要翻译： 通过在底部电极和/或电容器电介质上形成导电平滑层，形成由于减小了几何增强的电场和电极平滑而具有可靠性提高的MIM电容器。 在一个实施方案中，在由耐火氮化物形成的第一覆盖层上形成包括难熔金属或难熔金属富氮化物的层。 此外，可以在电容器电介质上形成第二难熔金属或难熔金属富氮的氮化物层。 平滑层也可以用于其它半导体器件，例如栅极电极和栅极电介质之间的晶体管。

公开(公告)号：US20090127587A1

公开(公告)日：2009-05-21

申请号：US12361944

申请日：2009-01-29

申请人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

发明人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

IPC分类号： H01L29/78 ,  H01L29/86 ,  H01L25/07

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

摘要翻译： 可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域 （106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。 电介质层（110）包括可调阶梯结构（127）。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。 电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

公开(公告)号：US07528015B2

公开(公告)日：2009-05-05

申请号：US11169962

申请日：2005-06-28

申请人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

发明人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

IPC分类号： H01L21/82 ,  H01L21/44 ,  H01L21/31

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A tunable antifuse element (102, 202, 204, 504, 952) and method of fabricating the tunable antifuse element, including a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) including the fabrication of one of a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a plurality of rupture regions (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

摘要翻译： 一种可调谐反熔断元件（102,202,204,504,952）和制造可调谐反熔丝元件的方法，包括在表面上形成有源区（106）的基片材料（101），具有 位于有源区域（106）上方的至少一部分，和设置在栅电极（104）和有源区域（106）之间的电介质层（110）。 介电层（110）包括制造可调阶梯结构（127）之一。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过介电层（110）的电流路径，并且多个断裂区域（130）中的电介质层（110）的破裂， 。 电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

公开(公告)号：US07700996B2

公开(公告)日：2010-04-20

申请号：US12361944

申请日：2009-01-29

申请人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

发明人： Patrice M. Parris ,  Weize Chen ,  John M. McKenna ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Richard J. De Souza

IPC分类号： H01L29/94

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L2924/0002 ,  Y10S438/981 ,  H01L2924/00

摘要： A tunable antifuse element (102, 202, 204, 504, 952) includes a substrate material (101) having an active area (106) formed in a surface, a gate electrode (104) having at least a portion positioned above the active area (106), and a dielectric layer (110) disposed between the gate electrode (104) and the active area (106). The dielectric layer (110) includes a tunable stepped structure (127). During operation, a voltage applied between the gate electrode (104) and the active area (106) creates a current path through the dielectric layer (110) and a rupture of the dielectric layer (110) in a rupture region (130). The dielectric layer (110) is tunable by varying the stepped layer thicknesses and the geometry of the layer.

摘要翻译： 可调谐反熔断元件（102,202,204,504,952）包括具有形成在表面中的有源区域（106）的基板材料（101），栅电极（104），其至少部分位于有源区域 （106）和设置在栅电极（104）和有源区（106）之间的电介质层（110）。 电介质层（110）包括可调阶梯结构（127）。 在操作期间，施加在栅极电极（104）和有源区域（106）之间的电压产生穿过电介质层（110）的电流路径以及在破裂区域（130）中电介质层（110）的破裂。 电介质层（110）可以通过改变阶梯层厚度和层的几何形状来调节。

公开(公告)号：US07211477B2

公开(公告)日：2007-05-01

申请号：US11124469

申请日：2005-05-06

申请人： Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

公开(公告)号：US06787858B2

公开(公告)日：2004-09-07

申请号：US10272336

申请日：2002-10-16

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice Parris

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice Parris

IPC分类号： H01L2994

CPC分类号： H01L27/0921 ,  H01L21/761 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

摘要翻译： 结构保护CMOS逻辑免受由功率器件的感应开关引起的衬底少数载流子注入。 单个集成电路（IC）支持一个或多个功率MOSFET和一个或多个CMOS逻辑阵列。 在功率MOSFET的漏极和CMOS逻辑阵列之间形成高度掺杂的环，以为注入的少数载流子提供低电阻的接地路径。 在CMOS逻辑下是高掺杂掩埋层，以形成注入的少数载流子的高复合区域。 一个或多个CMOS器件形成在掩埋层上方。 衬底是电阻的，并且注入的电流被衰减。 CMOS器件休息的阱为注入的少数载流子形成低电阻接地层。

公开(公告)号：US07301187B2

公开(公告)日：2007-11-27

申请号：US11689313

申请日：2007-03-21

申请人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

摘要翻译： 为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。 源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开 ）和源极（70,70'）或漏极（76,76'）。 与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。 穿过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。 随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分 ，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。 因此，BVdss增加。

公开(公告)号：US06828650B2

公开(公告)日：2004-12-07

申请号：US10160940

申请日：2002-05-31

申请人： Edouard de Frésart ,  Patrice Parris ,  Richard J De Souza ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Xin Lin

发明人： Edouard de Frésart ,  Patrice Parris ,  Richard J De Souza ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Xin Lin

IPC分类号： H01L2900

CPC分类号： H01L29/0692 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/7322

摘要： A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

摘要翻译： 双极结晶体管（BJT），通过使用沟槽回拉结构减少电流增益的变化。 沟槽回拉结构由沟槽和有源区组成。 沟槽通过增加载流子必须在发射极和基极之间行进的距离来减小发射极 - 基极区域中的复合。 沟槽还通过减少从发射体注入的电子暴露的界面陷阱的量来减少重组。 此外，从发射极拉回沟槽，允许从发射极的侧壁注入的电子能够有助于整个注入的发射极电流的有源区。 该结构提供与发射极和基极之间没有沟槽的器件相同的电流能力和电流增益，同时减小电流增益变化。