公开(公告)号：US06787858B2

公开(公告)日：2004-09-07

申请号：US10272336

申请日：2002-10-16

申请人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice Parris

发明人： Moaniss Zitouni ,  Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice Parris

IPC分类号： H01L2994

CPC分类号： H01L27/0921 ,  H01L21/761 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure protects CMOS logic from substrate minority carrier injection caused by the inductive switching of a power device. A single Integrated Circuit (IC) supports one or more power MOSFETs and one or more arrays of CMOS logic. A highly doped ring is formed between the drain of the power MOSFET and the CMOS logic array to provide a low resistance path to ground for the injected minority carriers. Under the CMOS logic is a highly doped buried layer to form a region of high recombination for the injected minority carriers. One or more CMOS devices are formed above the buried layer. The substrate is a resistive and the injected current is attenuated. The well in which the CMOS devices rest forms a low resistance ground plane for the injected minority carriers.

摘要翻译： 结构保护CMOS逻辑免受由功率器件的感应开关引起的衬底少数载流子注入。 单个集成电路（IC）支持一个或多个功率MOSFET和一个或多个CMOS逻辑阵列。 在功率MOSFET的漏极和CMOS逻辑阵列之间形成高度掺杂的环，以为注入的少数载流子提供低电阻的接地路径。 在CMOS逻辑下是高掺杂掩埋层，以形成注入的少数载流子的高复合区域。 一个或多个CMOS器件形成在掩埋层上方。 衬底是电阻的，并且注入的电流被衰减。 CMOS器件休息的阱为注入的少数载流子形成低电阻接地层。

公开(公告)号：US07211477B2

公开(公告)日：2007-05-01

申请号：US11124469

申请日：2005-05-06

申请人： Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. de Frésart ,  Richard J. De Souza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L21/336 ,  H01L21/8234

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

公开(公告)号：US06828650B2

公开(公告)日：2004-12-07

申请号：US10160940

申请日：2002-05-31

申请人： Edouard de Frésart ,  Patrice Parris ,  Richard J De Souza ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Xin Lin

发明人： Edouard de Frésart ,  Patrice Parris ,  Richard J De Souza ,  Jennifer H. Morrison ,  Moaniss Zitouni ,  Xin Lin

IPC分类号： H01L2900

CPC分类号： H01L29/0692 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/1004 ,  H01L29/7322

摘要： A Bipolar Junction Transistor (BJT) that reduces the variation in the current gain through the use of a trench pullback structure. The trench pullback structure is comprised of a trench and an active region. The trench reduces recombination in the emitter-base region through increasing the distance charge carriers must travel between the emitter and the base. The trench also reduces recombination by reducing the amount of interfacial traps that the electrons injected from the emitter are exposed to. Further, the trench is pulled back from the emitter allowing an active region where electrons injected from a sidewall of the emitter can contribute to the overall injected emitter current. This structure offers the same current capability and current gain as a device without the trench between the emitter and the base while reducing the current gain variation.

摘要翻译： 双极结晶体管（BJT），通过使用沟槽回拉结构减少电流增益的变化。 沟槽回拉结构由沟槽和有源区组成。 沟槽通过增加载流子必须在发射极和基极之间行进的距离来减小发射极 - 基极区域中的复合。 沟槽还通过减少从发射体注入的电子暴露的界面陷阱的量来减少重组。 此外，从发射极拉回沟槽，允许从发射极的侧壁注入的电子能够有助于整个注入的发射极电流的有源区。 该结构提供与发射极和基极之间没有沟槽的器件相同的电流能力和电流增益，同时减小电流增益变化。

公开(公告)号：US20060249751A1

公开(公告)日：2006-11-09

申请号：US11124469

申请日：2005-05-06

申请人： Edouard de Fresart ,  Richard De Souza ,  Xin Lin ,  Jennifer Morrison ,  Patrice Parris ,  Moaniss Zitouni

发明人： Edouard de Fresart ,  Richard De Souza ,  Xin Lin ,  Jennifer Morrison ,  Patrice Parris ,  Moaniss Zitouni

IPC分类号： H01L31/00

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

摘要翻译： 为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。 源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开 ）和源极（70,70'）或漏极（76,76'）。 与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。 穿过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。 随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分 ，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。 因此，BVdss增加。

公开(公告)号：US07301187B2

公开(公告)日：2007-11-27

申请号：US11689313

申请日：2007-03-21

申请人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

发明人： Edouard D. Defresart ,  Richard J. Desouza ,  Xin Lin ,  Jennifer H. Morrison ,  Patrice M. Parris ,  Moaniss Zitouni

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

摘要翻译： 为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。 源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开 ）和源极（70,70'）或漏极（76,76'）。 与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。 穿过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。 随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分 ，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。 因此，BVdss增加。

公开(公告)号：US20070158777A1

公开(公告)日：2007-07-12

申请号：US11689313

申请日：2007-03-21

申请人： Edouard de Fresart ,  Richard De Souza ,  Xin Lin ,  Jennifer Morrison ,  Patrice Parris ,  Moaniss Zitouni

发明人： Edouard de Fresart ,  Richard De Souza ,  Xin Lin ,  Jennifer Morrison ,  Patrice Parris ,  Moaniss Zitouni

IPC分类号： H01L23/58 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods and apparatus are provided for a MOSFET (50, 99, 199) exhibiting increased source-drain breakdown voltage (BVdss). Source (S) (70) and drain (D) (76) are spaced apart by a channel (90) underlying a gate (84) and one or more carrier drift spaces (92, 92′) serially located between the channel (90) and the source (70, 70′) or drain (76, 76′). A buried region (96, 96′) of the same conductivity type as the drift space (92, 92′) and the source (70, 70′) or drain (76, 76′) is provided below the drift space (92, 92′), separated therefrom in depth by a narrow gap (94, 94′) and ohmically coupled to the source (70, 70′) or drain (76, 76′). Current flow (110) through the drift space produces a potential difference (Vt) across this gap (94, 94′). As the S-D voltage (Vo) and current (109, Io) increase, this difference (Vt) induces high field conduction between the drift space (92, 92′) and the buried region (96, 96′) and diverts part (112, It) of the S-D current (109, Io) through the buried region (96, 96′) and away from the near surface portions of the drift space (92, 92′) where breakdown generally occurs. Thus, BVdss is increased.

摘要翻译： 为具有增加的源 - 漏击穿电压（BVdss）的MOSFET（50,99,199）提供了方法和装置。 源极（S）（70）和漏极（D）（76）通过栅极（84）下面的沟道（90）和串联地位于沟道（90）之间的一个或多个载流子漂移空间（92,92'）间隔开 ）和源极（70,70'）或漏极（76,76'）。 与漂移空间（92,92'）和源极（70,70'）或漏极（76,76'）相同的导电类型的掩埋区域（96,96'）设置在漂移空间（92,92'）的下方， 92'），通过狭窄的间隙（94,94'）深度地分离，并且与欧姆耦合到源极（70,70'）或漏极（76,76'）。 穿过漂移空间的电流（110）在该间隙（94,94'）上产生电位差（Vt）。 随着SD电压（Vo）和电流（109，Io）的增加，该差值（Vt）引起漂移空间（92,92'）和掩埋区域（96,96'）之间的高场导通，并且转移部分 ，It）通过掩埋区域（96,96'）并远离漂移空间（92,92'）的通常发生击穿的漂移空间（92,92'）的近表面部分的SD电流（109，Io）。 因此，BVdss增加。

公开(公告)号：US08344443B2

公开(公告)日：2013-01-01

申请号：US12109736

申请日：2008-04-25

申请人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L21/8247

CPC分类号： H01L29/7881 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).

摘要翻译： 单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213） 形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

公开(公告)号：US20090267127A1

公开(公告)日：2009-10-29

申请号：US12109736

申请日：2008-04-25

申请人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Richard J. De Souza ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L27/115 ,  H01L21/8247 ,  H01L21/8242

CPC分类号： H01L29/7881 ,  G11C16/10 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324

摘要： A single-poly non-volatile memory includes a PMOS select transistor (210) formed with a select gate (212), and P+ source and drain regions (211, 213) formed in a shared n-well region (240), a serially connected PMOS floating gate transistor (220) formed with part of a p-type floating gate layer (222) and P+ source and drain regions (221, 223) formed in the shared n-well region (240), and a coupling capacitor (230) formed over a p-well region (250) and connected to the PMOS floating gate transistor (220), where the coupling capacitor (230) includes a first capacitor plate formed with a second part of the p-type floating gate layer (222) and an underlying portion of the p-well region (250).

摘要翻译： 单多晶非易失性存储器包括形成有选择栅极（212）的PMOS选择晶体管（210），以及形成在共享的n阱区域（240）中的P +源区和漏区（211,213） 形成有形成在共用n阱区域（240）中的p型浮栅（222）和P +源区和漏区（221,223）的一部分的连接PMOS浮栅晶体管（220）和耦合电容器 230），其形成在p阱区（250）上并连接到PMOS浮栅晶体管（220），其中耦合电容器（230）包括形成有p型浮栅的第二部分的第一电容器板（ 222）和p阱区（250）的下层部分。

公开(公告)号：US09899500B2

公开(公告)日：2018-02-20

申请号：US14269825

申请日：2014-05-05

申请人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

发明人： Weize Chen ,  Xin Lin ,  Patrice M. Parris

IPC分类号： H01L29/66 ,  H01L29/872 ,  H01L29/10 ,  H01L27/06 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/66893 ,  H01L27/0629 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/08 ,  H01L29/1066 ,  H01L29/107 ,  H01L29/66143 ,  H01L29/872

摘要： A method of fabricating a Schottky diode having an integrated junction field-effect transistor (JFET) device includes forming a conduction path region in a semiconductor substrate along a conduction path of the Schottky diode. The conduction path region has a first conductivity type. A lateral boundary of an active area of the Schottky diode is defined by forming a well of a device isolating structure in the semiconductor substrate having a second conductivity type. An implant of dopant of the second conductivity type is conducted to form a buried JFET gate region in the semiconductor substrate under the conduction path region. The implant is configured to further form the device isolating structure in which the Schottky diode is disposed.

公开(公告)号：US09543379B2

公开(公告)日：2017-01-10

申请号：US14218330

申请日：2014-03-18

申请人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

发明人： Hongning Yang ,  Xin Lin ,  Zhihong Zhang ,  Jiang-Kai Zuo

IPC分类号： H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/36 ,  H01L21/8234 ,  H01L27/12

CPC分类号： H01L29/063 ,  H01L21/76283 ,  H01L21/823418 ,  H01L21/823481 ,  H01L27/1203 ,  H01L29/0619 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0688 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/1087 ,  H01L29/36 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66689 ,  H01L29/7823 ,  H01L29/7824 ,  H01L29/7835

摘要： A device includes a semiconductor substrate, source and drain regions disposed in the semiconductor substrate and having a first conductivity type, a body region disposed in the semiconductor substrate, having a second conductivity type, and in which the source region is disposed, a drift region disposed in the semiconductor substrate, having the first conductivity type, and through which charge carriers drift during operation upon application of a bias voltage between the source and drain regions, a device isolation region disposed in the semiconductor substrate and laterally surrounding the body region and the drift region, and a breakdown protection region disposed between the device isolation region and the body region and having the first conductivity type.

摘要翻译： 一种器件包括半导体衬底，设置在半导体衬底中并具有第一导电类型的源极和漏极区域，设置在半导体衬底中的体区，具有第二导电类型，并且其中设置源极区，漂移区 设置在具有第一导电类型的半导体衬底中，并且在施加源极和漏极区域之间的偏置电压时，电荷载体在工作期间漂移，设置在半导体衬底中并横向围绕身体区域的器件隔离区域和 漂移区域和设置在器件隔离区域和体区之间并具有第一导电类型的击穿保护区域。