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27 条记录 (耗时 0.018 秒)

    Control of high-k gate dielectric film composition profile for property optimization
    2.
    发明授权
    Control of high-k gate dielectric film composition profile for property optimization 有权
    控制高k栅极电介质膜组成轮廓的性能优化

    公开(公告)号：US07071519B2

    公开(公告)日：2006-07-04

    申请号：US10338310

    申请日：2003-01-08

    申请人： Luigi Colombo ,  Mark Visokay ,  James Joseph Chambers ,  Antonio Luis Pacheco Rotondaro

    发明人： Luigi Colombo ,  Mark Visokay ,  James Joseph Chambers ,  Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L29/94

    CPC分类号： H01L21/02271 ,  H01L21/28194 ,  H01L21/3142 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

    摘要： Methods and systems are disclosed that facilitate formation of dielectric layers having a particular composition profile by forming the dielectric layer as a number of sub-layers. The sub-layers are thin enough so that specific relative compositions can be achieved for each layer and, therefore, the sub-layers collectively yield a dielectric layer with a particular profile. The formation of individual sub layers is accomplished by controlling one or more processing parameters for a chemical vapor deposition process that affect relative compositions. Some processing parameters that can be employed include wafer temperature, pressure, and precursor flow rate.

    摘要翻译： 公开了通过将介电层形成多个子层来促进形成具有特定组成分布的电介质层的方法和系统。 子层足够薄，使得可以为每个层实现特定的相对组成，因此，子层共同产生具有特定轮廓的介电层。 单个子层的形成通过控制影响相对组成的化学气相沉积工艺的一个或多个处理参数来实现。 可采用的一些加工参数包括晶片温度，压力和前体流速。

    Work function control of metals
    3.
    发明授权
    Work function control of metals 有权
    金属工作功能控制

    公开(公告)号：US07291527B2

    公开(公告)日：2007-11-06

    申请号：US11220451

    申请日：2005-09-07

    申请人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

    发明人： James Joseph Chambers ,  Mark Robert Visokay ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/8238

    CPC分类号： H01L21/823842

    摘要： Forming metal gate transistors that have different work functions is disclosed. In one example, a first metal, which is a ‘mid gap’ metal, is manipulated in first and second regions by second and third metals, respectively, to move the work function of the first metal in opposite directions in the different regions. The resulting work functions in the different regions correspond to that of different types of the transistors that are to be formed.

    摘要翻译： 公开了具有不同功函数的金属栅极晶体管。 在一个示例中，第一金属是“中间间隙”金属，分别在第一和第二区域中被第二和第三金属操纵，以在不同区域中沿相反方向移动第一金属的功函数。 在不同区域中产生的功函数对应于将要形成的不同类型的晶体管。

    Methods for sputter deposition of high-k dielectric films
    4.
    发明授权
    Methods for sputter deposition of high-k dielectric films 有权
    溅射沉积高k电介质膜的方法

    公开(公告)号：US06750126B1

    公开(公告)日：2004-06-15

    申请号：US10338276

    申请日：2003-01-08

    申请人： Mark Visokay ,  James Joseph Chambers ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

    发明人： Mark Visokay ,  James Joseph Chambers ,  Luigi Colombo ,  Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L213205

    CPC分类号： H01L21/28202 ,  H01L21/28035 ,  H01L21/28194 ,  H01L21/314 ,  H01L21/3143 ,  H01L21/31645 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/6659

    摘要： Methods are disclosed for fabricating transistor gate structures and high-k dielectric layers therefor by sputter deposition, in which nitridation and/or oxidation or other adverse reaction of the semiconductor material is reduced or minimized by reducing the bombardment of the semiconductor body by positively charged reactive ions such as oxygen ions or nitrogen ions during the sputter deposition process. The sputtering operation may be a two-step process in which ionic bombardment of the semiconductor material is minimized in an initial deposition step to form a first layer portion covering the semiconductor body, and the second step completes the desired high-k dielectric layer. Mitigation of unwanted nitridation and/or oxidation or other adverse reaction is achieved through one, some, or all of high sputtering deposition pressure, repulsive wafer biasing, increased wafer-plasma spacing, low partial pressures for reactant gases, and low sputtering powers or power densities.

    摘要翻译： 公开了用于通过溅射沉积来制造晶体管栅极结构和高k电介质层的方法，其中半导体材料的氮化和/或氧化或其它不利反应被减小或最小化，通过减少半导体主体的带正电荷的反应 离子如氧离子或氮离子在溅射沉积过程中。 溅射操作可以是在初始沉积步骤中使半导体材料的离子轰击最小化以形成覆盖半导体本体的第一层部分的两步法，并且第二步骤完成所需的高k电介质层。 通过高溅射沉积压力，排斥晶片偏置，增加的晶片 - 等离子体间隔，反应气体的低分压以及低溅射功率或功率的一种，一些或全部来实现减少不希望的氮化和/或氧化或其它不利反应 密度

    Method for the selective removal of high-k dielectrics
    5.
    发明授权
    Method for the selective removal of high-k dielectrics 有权
    选择性去除高k电介质的方法

    公开(公告)号：US06656852B2

    公开(公告)日：2003-12-02

    申请号：US10006081

    申请日：2001-12-06

    申请人： Antonio Luis Pacheco Rotondaro ,  James Joseph Chambers

    发明人： Antonio Luis Pacheco Rotondaro ,  James Joseph Chambers

    IPC分类号： H01L21302

    CPC分类号： H01L21/28194 ,  H01L21/31111 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

    摘要： One aspect of the invention relates to a method of etching a high-k dielectric. The method involves removing an exposed portion of a high-k dielectric layer from a substrate by wet etching with a solution comprising water, a strong acid, an oxidizing agent, and a fluorine compound. The etching solution provides selectivity towards the high-k film against insulating materials and polysilicon and is therefore useful in manufacturing FETs.

    摘要翻译： 本发明的一个方面涉及一种蚀刻高k电介质的方法。 该方法包括通过用包含水，强酸，氧化剂和氟化合物的溶液的湿蚀刻从基底去除高k电介质层的暴露部分。 蚀刻溶液提供了对绝缘材料和多晶硅的高k膜的选择性，因此可用于制造FET。

    Method to prevent defects on SRAM cells that incorporate selective epitaxial regions
    6.
    发明申请
    Method to prevent defects on SRAM cells that incorporate selective epitaxial regions 有权
    防止并入选择性外延区域的SRAM单元上的缺陷的方法

    公开(公告)号：US20070290192A1

    公开(公告)日：2007-12-20

    申请号：US11453190

    申请日：2006-06-14

    申请人： Antonio Luis Pacheco Rotondaro

    发明人： Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L31/00

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823418 ,  H01L27/088 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/66636 ,  H01L29/7848

    摘要： An SRAM device and method of forming MOS transistors of the device having reduced defects associated with selective epitaxial growth in moat tip regions is discussed. The SRAM device comprises a core region and a logic region, logic transistors within the logic region of the SRAM, and selective epitaxial regions grown on both source and drain regions; and memory cell transistors within the core region of the SRAM, and having the selective epitaxial regions grown on only one of the source and drain regions. One method of forming the MOS transistors of the SRAM cell comprises forming a gate structure over a first conductivity type substrate to define a channel therein, masking one of the source and drain regions in the core region, forming a recess in the substrate of the unmasked side of the channel, epitaxially growing SiGe in the recess, removing the mask, and forming the source and drain extension regions in source/drain regions.

    摘要翻译： 讨论了一种SRAM器件和形成具有减少的与护套护耳区域中的选择性外延生长有关的缺陷的器件的MOS晶体管的方法。 SRAM器件包括核心区域和逻辑区域，在SRAM的逻辑区域内的逻辑晶体管以及在源极和漏极区域上生长的选择性外延区域; 以及在SRAM的核心区域内的存储单元晶体管，并且仅在源极和漏极区域之一上生长选择性外延区域。 形成SRAM单元的MOS晶体管的一种方法包括在第一导电类型衬底上形成栅极结构以在其中限定沟道，掩蔽芯区域中的源区和漏区之一，在未屏蔽的衬底中形成凹陷 在沟槽中外延生长SiGe，去除掩模，以及在源极/漏极区域中形成源极和漏极延伸区域。

    Systems and methods for low leakage strained-channel transistor
    7.
    发明授权
    Systems and methods for low leakage strained-channel transistor 有权
    低泄漏应变通道晶体管的系统和方法

    公开(公告)号：US07026232B1

    公开(公告)日：2006-04-11

    申请号：US11021020

    申请日：2004-12-23

    申请人： Elisabeth Marley Koontz ,  Antonio Luis Pacheco Rotondaro

    发明人： Elisabeth Marley Koontz ,  Antonio Luis Pacheco Rotondaro

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L21/76 ,  H01L21/336

    CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636

    摘要： The present invention facilitates semiconductor fabrication by providing methods of fabrication that mitigate leakage and apply strain to channel regions of transistor devices. A semiconductor device having gate structures, channel regions, and active regions is provided (102). Extension regions of a first type of conductivity are formed within the active regions (104). Recesses are then formed within a portion of the active regions (106). Second type recess structures are formed (108) within the recesses, wherein the second type recess structures have a second type of conductivity opposite the first type and are comprised of a strain inducing material. Then, first type recess structures are formed (110) within the recesses and on the second type recess structures, wherein the first type recess structures have the first type of conductivity and are comprised of a strain inducing material.

    摘要翻译： 本发明通过提供减少泄漏并施加应变到晶体管器件的沟道区的制造方法来促进半导体制造。 提供具有栅极结构，沟道区和有源区的半导体器件（102）。 在有源区（104）内形成第一类导电性的延伸区。 然后在有源区域（106）的一部分内形成凹陷。 在凹部内形成有第二类型的凹部结构（108），其中第二类型的凹部结构具有与第一类型相反的第二类型的导电性并且由应变诱导材料构成。 然后，在凹部内和第二类型的凹部结构上形成第一类型的凹部结构（110），其中第一类型的凹部结构具有第一类型的导电性并且由应变诱导材料构成。