公开(公告)号：US11031241B2

公开(公告)日：2021-06-08

申请号：US16704124

申请日：2019-12-05

Applicant: Applied Materials, Inc.

Inventor： Yi-Chiau Huang ,  Errol Antonio C Sanchez

IPC: H01L21/02

Abstract: Methods for forming films during semiconductor device fabrication by soaking a substrate in dopant are discussed herein. The dopant soak is performed in a process chamber using at least one dopant precursor for a predetermined period of time to form a dopant layer on the substrate. The process chamber is subsequently purged of the at least one dopant precursor. At least one film precursor is introduced into the process chamber after the process chamber is purged. A film is epitaxially formed on the substrate to have at least one of a target resistivity, dopant concentration, and/or thickness. Post-processing operations can include annealing or patterning the semiconductor film, or depositing additional layers thereon.

公开(公告)号：US11649560B2

公开(公告)日：2023-05-16

申请号：US16530641

申请日：2019-08-02

Applicant: Applied Materials, Inc.

Inventor： Errol Antonio C Sanchez ,  Mark J. Saly ,  Schubert Chu ,  Abhishek Dube ,  Srividya Natarajan

IPC: H01L21/00 ,  C30B29/54 ,  C07F9/50 ,  H01L29/08 ,  H01L21/02 ,  C30B25/02

CPC classification number: C30B29/54 ,  C07F9/5009 ,  C30B25/02 ,  H01L21/0262 ,  H01L21/02521 ,  H01L29/0843

Abstract: Embodiments generally relate to methods for depositing silicon-phosphorous materials, and more specifically, relate to using silicon-phosphorous compounds in vapor deposition processes (e.g., epitaxy, CVD, or ALD) to deposit silicon-phosphorous materials. In one or more embodiments, a method for forming a silicon-phosphorous material on a substrate is provided and includes exposing the substrate to a deposition gas containing one or more silicon-phosphorous compounds during a deposition process and depositing a film containing the silicon-phosphorous material on the substrate. The silicon-phosphorous compound has the chemical formula [(R3-vHvSi)—(R2-wHwSi)n]xPHyR′z, where each instance of R and each instance of R′ are independently an alkyl or a halogen, n is 0, 1, or 2; v is 0, 1, 2, or 3; w is 0, 1, or 2; x is 1, 2, or 3; y is 0, 1, or 2; z is 0, 1, or 2, and where x+y+z=3.

公开(公告)号：US12091749B2

公开(公告)日：2024-09-17

申请号：US17317565

申请日：2021-05-11

Applicant: Applied Materials, Inc.

Inventor： Tetsuya Ishikawa ,  Swaminathan T. Srinivasan ,  Matthias Bauer ,  Manjunath Subbanna ,  Ala Moradian ,  Kartik Bhupendra Shah ,  Errol Antonio C Sanchez ,  Michael R. Rice ,  Peter Reimer ,  Marc Shull

IPC: C30B25/14 ,  C23C16/44 ,  C23C16/458 ,  C23C16/46 ,  C23C16/52 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16

CPC classification number: C23C16/4408 ,  C23C16/4584 ,  C23C16/46 ,  C23C16/52 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16

Abstract: Embodiments described herein include processes and apparatuses relate to epitaxial deposition. A method for epitaxially depositing a material is provided and includes positioning a substrate on a substrate support surface of a susceptor within a process volume of a chamber body, where the process volume contains upper and lower chamber regions. The method includes flowing a process gas containing one or more chemical precursors from an upper gas inlet on a first side of the chamber body, across the substrate, and to an upper gas outlet on a second side of the chamber body, flowing a purge gas from a lower gas inlet on the first side of the chamber body, across the lower surface of the susceptor, and to a lower gas outlet on the second side of the chamber body, and maintaining a pressure of the lower chamber region greater than a pressure of the upper chamber region.

公开(公告)号：US12015042B2

公开(公告)日：2024-06-18

申请号：US16797807

申请日：2020-02-21

Applicant: Applied Materials, Inc.

Inventor： Papo Chen ,  Schubert Chu ,  Errol Antonio C Sanchez ,  John Timothy Boland ,  Zhiyuan Ye ,  Lori Washington ,  Xianzhi Tao ,  Yi-Chiau Huang ,  Chen-Ying Wu

IPC: H01L27/146 ,  H01L31/18

CPC classification number: H01L27/14636 ,  H01L27/1463 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14689 ,  H01L31/1892

Abstract: A method of fabricating a semiconductor device includes forming an interconnect structure over a front side of a sensor substrate, thinning the sensor substrate from a back side of the sensor substrate, etching trenches into the sensor substrate, pre-cleaning an exposed surface of the sensor substrate, epitaxially growing a charge layer directly on the pre-cleaned exposed surface of the sensor substrate, and forming isolation structures within the etched trenches.