公开(公告)号：US20190326110A1

公开(公告)日：2019-10-24

申请号：US16462513

申请日：2017-11-16

Applicant: Applied Materials, Inc.

Inventor： Milind GADRE ,  Shaunak MUKHERJEE ,  Praket P. JHA ,  Deenesh PADHI ,  Ziqing DUAN ,  Abhijit B. MALLICK

IPC: H01L21/02 ,  C23C16/34 ,  H01L21/768

Abstract: Embodiments disclosed herein relate to methods for forming memory devices, and more specifically to improved methods for forming a dielectric encapsulation layer over a memory material in a memory device. In one embodiment, the method includes thermally depositing a first material over a memory material at a temperature less than the temperature of the thermal budget of the memory material, exposing the first material to nitrogen plasma to incorporate nitrogen in the first material, and repeating the thermal deposition and nitrogen plasma operations to form a hermetic, conformal dielectric encapsulation layer over the memory material. Thus, a memory device having a hermetic, conformal dielectric encapsulation layer over the memory material is formed.

公开(公告)号：US20180330951A1

公开(公告)日：2018-11-15

申请号：US15977388

申请日：2018-05-11

Applicant: Applied Materials, Inc.

Inventor： Prashant Kumar KULSHRESHTHA ,  Jiarui WANG ,  Kwangduk Douglas LEE ,  Milind GADRE ,  Xiaoquan MIN ,  Paul CONNORS

IPC: H01L21/225 ,  G03F1/38

Abstract: Embodiments of the present disclosure generally relate to methods and apparatus for depositing metal silicide layers on substrates and chamber components. In one embodiment, a method of forming a hardmask includes positioning the substrate having a target layer within a processing chamber, forming a seed layer comprising metal silicide on the target layer and depositing a tungsten-based bulk layer on the seed layer, wherein the metal silicide layer and the tungsten-based bulk layer form the hardmask. In another embodiment, a method of conditioning the components of a plasma processing chamber includes flowing an inert gas comprising argon or helium from a gas applicator into the plasma processing chamber, exposing a substrate support to a plasma within the plasma processing chamber and forming a seasoning layer including metal silicide on an aluminum-based surface of the substrate support.

公开(公告)号：US20190074176A1

公开(公告)日：2019-03-07

申请号：US16120867

申请日：2018-09-04

Applicant: Applied Materials, Inc.

Inventor： Lei GUO ,  Praket P. JHA ,  Milind GADRE ,  Deenesh PADHI ,  Tza-Jing GUNG

IPC: H01L21/02 ,  C23C16/40 ,  C23C16/50

Abstract: Aspects disclosed herein relate to methods of depositing pure silicon oxide on a substrate using Octamethylcyclotetrasiloxane (OMCTS) precursor. In one aspect, the method generally includes positioning a substrate in a processing chamber, introducing an oxygen-containing gas into the processing chamber, introducing OMCTS precursor into the processing chamber, and reacting the oxygen-containing gas and the OMCTS precursor to remove carbon and deposit pure silicon oxide on the substrate.

公开(公告)号：US20170353994A1

公开(公告)日：2017-12-07

申请号：US15174526

申请日：2016-06-06

Applicant: Applied Materials, Inc.

Inventor： Sam H. KIM ,  Yuxing ZHANG ,  Milind GADRE ,  Sanjeev BALUJA

IPC: H05B1/02 ,  H05B3/24

CPC classification number: H05B1/0233 ,  H05B3/24

Abstract: A pedestal is provided that includes a body, a heater embedded in the body, a support pocket formed within the body having a surface disposed in a first plane, a peripheral surface disposed in a second plane surrounding the support pocket, and a plurality of centering tabs positioned between the support pocket and the peripheral surface, each of the centering tabs having a surface disposed in a third plane that is between both of the first and second planes.

公开(公告)号：US20190341285A1

公开(公告)日：2019-11-07

申请号：US16377010

申请日：2019-04-05

Applicant: Applied Materials, Inc.

Inventor： Milind GADRE

IPC: H01L21/67 ,  H01J37/32

Abstract: A method and apparatus for detecting and correcting incoming substrate deformation is disclosed. Substrates are positioned in a first process chamber, where the presence and type of substrate bow is detected. Based upon the detection of substrate bow, and a determination of whether the substrate has a compressive bow or a tensile bow, a substrate processing program is selected for execution. The substrate processing program can be executed in the first process chamber or in a second process chamber to correct or alleviate the bow prior to or during further processing of the substrate.

公开(公告)号：US20180350596A1

公开(公告)日：2018-12-06

申请号：US15976945

申请日：2018-05-11

Applicant: Applied Materials, Inc.

Inventor： Milind GADRE ,  Praket P. JHA ,  Deenesh PADHI

IPC: H01L21/02

CPC classification number: H01L21/02532 ,  C23C16/24 ,  C23C16/46 ,  C23C16/509 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/0262

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon (a-Si) layers on a semiconductor substrate. In one implementation, a method is provided. The method comprises generating a pressure within a processing volume between 2 Torr and 60 Torr. The method further comprises heating a substrate in the processing volume to a temperature between 300 degrees Celsius and 550 degrees Celsius. The method further comprises flowing a silane-containing gas mixture into the processing volume having the substrate positioned therein. The method further comprises flowing a borane-containing gas mixture into the processing volume having the substrate positioned therein and depositing a boron-doped amorphous silicon layer on the substrate.

公开(公告)号：US20180076042A1

公开(公告)日：2018-03-15

申请号：US15695269

申请日：2017-09-05

Applicant: Applied Materials, Inc.

Inventor： Rui CHENG ,  Ziqing DUAN ,  Milind GADRE ,  Praket P. JHA ,  Abhijit Basu MALLICK ,  Deenesh PADHI

IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/02 ,  H01L21/3105 ,  C23C16/30

CPC classification number: H01L21/28525 ,  C23C16/045 ,  C23C16/24 ,  C23C16/30 ,  H01L21/02381 ,  H01L21/02389 ,  H01L21/02488 ,  H01L21/02494 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/02592 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02642 ,  H01L21/0337 ,  H01L21/3105 ,  H01L21/32055

Abstract: Implementations described herein generally relate to the fabrication of integrated circuits and particularly to the deposition of a boron-doped amorphous silicon layers on a semiconductor substrate. In one implementation, a method of forming a boron-doped amorphous silicon layer on a substrate is provided. The method comprises depositing a predetermined thickness of a sacrificial dielectric layer over a substrate, forming patterned features on the substrate by removing portions of the sacrificial dielectric layer to expose an upper surface of the substrate, depositing conformally a predetermined thickness of a boron-doped amorphous silicon layer on the patterned features and the exposed upper surface of the substrate and selectively removing the boron-doped amorphous silicon layer from an upper surface of the patterned features and the upper surface of the substrate using an anisotropic etching process to provide the patterned features filled within sidewall spacers formed from the boron-doped amorphous silicon layer.