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公开(公告)号:US11776835B2
公开(公告)日:2023-10-03
申请号:US17036048
申请日:2020-09-29
Applicant: Applied Materials, Inc.
Inventor: Zheng John Ye , Daemian Raj Benjamin Raj , Rana Howlader , Abhigyan Keshri , Sanjay G. Kamath , Dmitry A. Dzilno , Juan Carlos Rocha-Alvarez , Shailendra Srivastava , Kristopher R. Enslow , Xinhai Han , Deenesh Padhi , Edward P. Hammond
IPC: H01L21/683 , H01L21/67 , H01J37/32
CPC classification number: H01L21/6833 , H01J37/32183 , H01J37/32697 , H01J37/32724 , H01L21/67069 , H01L21/67103
Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.
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公开(公告)号:US11371136B2
公开(公告)日:2022-06-28
申请号:US16647794
申请日:2018-09-19
Applicant: Applied Materials, Inc.
Inventor: Bhaskar Jyoti Bhuyan , Mark Saly , David Thompson , Lakmal C. Kalutarage , Rana Howlader
IPC: H01L21/31 , C23C16/04 , C23C16/455 , H01L21/02
Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.
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公开(公告)号:US20200216949A1
公开(公告)日:2020-07-09
申请号:US16647794
申请日:2018-09-19
Applicant: Applied Materials, Inc.
Inventor: Bhaskar Jyoti Bhuyan , Mark Saly , David Thompson , Lakmal C. Kalutarage , Rana Howlader
IPC: C23C16/04 , C23C16/455 , H01L21/02
Abstract: Methods of depositing a film selectively onto a first substrate surface relative to a second substrate surface are described. The methods include exposing a substrate to a blocking molecule to selectively deposit a blocking layer on the first surface. The blocking layer is exposed to a polymer initiator to form a networked blocking layer. A layer is selectively formed on the second surface. The blocking layer inhibits deposition on the first surface. The networked layer may then optionally be removed.
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公开(公告)号:US20220119952A1
公开(公告)日:2022-04-21
申请号:US17074961
申请日:2020-10-20
Applicant: Applied Materials, Inc.
Inventor: Rana Howlader , Hang Yu , Madhu Santosh Kumar Mutyala , Zheng John Ye , Abhigyan Keshri , Sanjay Kamath , Daemian Raj Benjamin Raj , Deenesh Padhi
IPC: C23C16/50 , C23C16/40 , H01L21/02 , C23C16/458 , C23C16/455
Abstract: Exemplary deposition methods may include electrostatically chucking a semiconductor substrate at a first voltage within a processing region of a semiconductor processing chamber. The methods may include performing a deposition process. The deposition process may include forming a plasma within the processing region of the semiconductor processing chamber. The methods may include halting formation of the plasma within the semiconductor processing chamber. The methods may include, simultaneously with the halting, increasing the first voltage of electrostatic chucking to a second voltage. The methods may include purging the processing region of the semiconductor processing chamber.
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公开(公告)号:US20220102179A1
公开(公告)日:2022-03-31
申请号:US17036048
申请日:2020-09-29
Applicant: Applied Materials, Inc.
Inventor: Zheng John Ye , Daemian Raj Benjamin Raj , Rana Howlader , Abhigyan Keshri , Sanjay G. Kamath , Dmitry A. Dzilno , Juan Carlos Rocha-Alvarez , Shailendra Srivastava , Kristopher R. Enslow , Xinhai Han , Deenesh Padhi , Edward P. Hammond
IPC: H01L21/683 , H01L21/67 , H01J37/32
Abstract: Exemplary semiconductor processing systems may include a processing chamber and an electrostatic chuck disposed at least partially within the processing chamber. The electrostatic chuck may include at least one electrode and a heater. A semiconductor processing system may include a power supply to provide a signal to the electrode to provide electrostatic force to secure a substrate to the electrostatic chuck. The system may also include a filter communicatively coupled between the power supply and the electrode. The filter is configured to remove or reduce noise introduced into the chucking signal by operating the heater while the electrostatic force on the substrate is maintained. The filter may include active circuitry, passive circuitry, or both, and may include an adjustment circuit to set the gain of the filter so that an output signal level from the filter corresponds to an input signal level for the filter.
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6.
公开(公告)号:US20170092533A1
公开(公告)日:2017-03-30
申请号:US14957380
申请日:2015-12-02
Applicant: APPLIED MATERIALS, INC.
Inventor: Tapash Chakraborty , Mark Saly , Rana Howlader , Eswaranand Venkatasubramanian , Prerna Sonthalia Goradia , Robert Jan Visser , David Thompson
IPC: H01L21/768 , H01L21/321 , H01L21/02
CPC classification number: H01L21/76802 , H01L21/02164 , H01L21/02167 , H01L21/0217 , H01L21/0226 , H01L21/0228 , H01L21/02307 , H01L21/32 , H01L21/321 , H01L21/3212 , H01L21/76829 , H01L21/7684 , H01L21/76877 , H01L21/76883
Abstract: Methods of selectively depositing a patterned layer on exposed dielectric material but not on exposed metal surfaces are described. A self-assembled monolayer (SAM) is deposited using phosphonic acids. Molecules of the self-assembled monolayer include a head moiety and a tail moiety, the head moiety forming a bond with the exposed metal portion and the tail moiety extending away from the patterned substrate and reducing the deposition rate of the patterned layer above the exposed metal portion relative to the deposition rate of the patterned layer above the exposed dielectric portion. A dielectric layer is subsequently deposited by atomic layer deposition (ALD) which cannot initiate in regions covered with the SAM in embodiments.
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