公开(公告)号：US06985021B1

公开(公告)日：2006-01-10

申请号：US10652521

申请日：2003-08-29

申请人： Arch Zaliznyak ,  William Bereza ,  Henry Lui ,  Chong Lee ,  Rakesh Patel

发明人： Arch Zaliznyak ,  William Bereza ,  Henry Lui ,  Chong Lee ,  Rakesh Patel

IPC分类号： H03F3/45

CPC分类号： H03F3/45475 ,  H03F3/4521 ,  H03F3/45928 ,  H03F2200/513 ,  H03F2203/45088 ,  H03F2203/45101 ,  H03F2203/45136 ,  H03F2203/45236 ,  H03F2203/45366 ,  H03F2203/45544 ,  H03F2203/45561 ,  H03F2203/45586 ,  H03F2203/45592 ,  H03F2203/45594 ,  H03F2203/45616 ,  H03K19/003

摘要： Circuitry is provided that conditions a differential input signal such that when the signal is received by a multi-standard differential input buffer, the buffer is able to process the conditioned signal without pronounced increases in propagation delay, thereby keeping signal jitter to a minimum. The circuitry further enables input buffers to operate according to desired operating parameters even when the supply voltage powering the input buffer is relatively low. The circuitry operates by shifting the common-mode voltage to a range that puts the input buffer in a favorable common-mode voltage range of operation. The circuitry may be coupled with a programmably controlled amplifier that amplifies the amplitude of the conditioned differential signal prior to being received by the input buffer. Amplifying the signal prevents problems typically associated with data-dependent jitter and intersymbol interference by boosting the voltage amplitude to a level that is readily processed by the input buffer.

摘要翻译： 提供电路，其规定差分输入信号，使得当信号被多标准差分输入缓冲器接收时，缓冲器能够处理调节后的信号而传播延迟不会明显增加，从而将信号抖动保持在最小。 该电路还使输入缓冲器能够根据期望的操作参数进行操作，即使为输入缓冲器供电的电源电压相对较低。 电路通过将共模电压移动到使输入缓冲器处于有利的共模电压操作范围的范围来工作。 电路可以与可编程控制的放大器耦合，放大器在由输入缓冲器接收之前放大经调节的差分信号的幅度。 通过将电压幅度升高到输入缓冲器容易处理的电平，放大信号可防止通常与数据相关的抖动和符号间干扰相关的问题。

公开(公告)号：US07639993B1

公开(公告)日：2009-12-29

申请号：US11295391

申请日：2005-12-05

申请人： Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  William Bereza ,  Wilson Wong ,  Tim Tri Hoang

发明人： Sergey Yuryevich Shumarayev ,  Rakesh Patel ,  William Bereza ,  Wilson Wong ,  Tim Tri Hoang

IPC分类号： H04B1/04

CPC分类号： H04L7/033

摘要： The various components of transceiver circuitry on an integrated circuit are put together in various ways for purposes of being supplied with power to help prevent noise propagation between the groups. In the case of multi-channel transceiver circuitry there can be various amounts of power supply sharing between similar groups in multiple channels.

摘要翻译： 集成电路中的收发器电路的各种组件以各种方式放在一起，以便被提供电力以帮助防止组之间的噪声传播。 在多通道收发器电路的情况下，可以在多个通道中的类似组之间存在各种数量的电源共享。

公开(公告)号：US20070019766A1

公开(公告)日：2007-01-25

申请号：US11432419

申请日：2006-05-10

申请人： William Bereza ,  Shoujun Wang ,  Rakesh Patel

发明人： William Bereza ,  Shoujun Wang ,  Rakesh Patel

IPC分类号： H04L7/00

CPC分类号： H03L7/07 ,  H03K19/1774 ,  H03K19/17744 ,  H03M9/00

摘要： Data transmitter circuitry on a programmable logic device (“PLD”) includes a plurality of channels of serializer circuitry, and a plurality of clock multiplier units (“CMUs”), each of which is associated with a respective subplurality of the serializer channels. Each CMU includes multiple reference clock signal sources, multiple phase-locked loop (“PLL”) circuits, and circuitry for allowing any PLL to get its reference input from any of the reference sources. Raw and centrally processed clock signals produced by each CMU are distributed to the serializer channels associated with that CMU and, at least in the case of the centrally processed signals, to the serializer channels associated with another CMU. The signal that controls release of parallel data to each serializer channel can be an output signal of that channel, or it can be an output signal of any CMU from which that channel can get a clock signal.

公开(公告)号：US07848402B1

公开(公告)日：2010-12-07

申请号：US11239703

申请日：2005-09-29

申请人： Shoujun Wang ,  Yuming Tao ,  Tad Kwasniewski ,  William Bereza

发明人： Shoujun Wang ,  Yuming Tao ,  Tad Kwasniewski ,  William Bereza

IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

CPC分类号： H04L25/03878 ,  H03H15/00 ,  H04L25/0276 ,  H04L25/0288 ,  H04L25/03025 ,  H04L25/03038 ,  H04L25/03057 ,  H04L2025/03471

摘要： Methods and circuits are provided for producing phase-adjusted pre-emphasis and equalization. In applications in which little or no phase distortion occurs during signal transmission, propagation, or reception, linear-phase pre-emphasis or equalization can be used to reduce or eliminate phase distortion introduced by the pre-emphasis or equalization. Linear phase, constant group delay FIR filters or circuits may have odd numbers of coefficients symmetrical about the middle coefficient. In applications in which signal phase distortion occurs, linear phase or non-linear phase pre-emphasis or equalization can be used to reduce or compensate for the phase distortion. Phase compensation may be effected using FIR pre-emphasis and equalization filters and circuits. Non-linear phase FIR filters may have different numbers and combinations of coefficients.

摘要翻译： 提供了用于产生相位调整预加重和均衡的方法和电路。 在信号传输，传播或接收期间发生很少或没有相位失真的应用中，可以使用线性相位预加重或均衡来减少或消除由预加重或均衡引入的相位失真。 线性相位，常数组延迟FIR滤波器或电路可能具有关于中间系数对称的奇数系数。 在发生信号相位失真的应用中，可以使用线性相位或非线性相位预加重或均衡来减少或补偿相位失真。 可以使用FIR预加重和均衡滤波器和电路实现相位补偿。 非线性相位FIR滤波器可以具有不同的数字和系数的组合。

公开(公告)号：US07619460B2

公开(公告)日：2009-11-17

申请号：US12011065

申请日：2008-01-23

申请人： Haitao Mei ,  Shoujun Wang ,  William Bereza ,  Mirza Baig

发明人： Haitao Mei ,  Shoujun Wang ,  William Bereza ,  Mirza Baig

IPC分类号： H03L5/00

CPC分类号： H03K3/35613 ,  H04L25/0272 ,  H04L25/0294

摘要： A reference clock receiver structure according to the invention is provided. The structure preferably includes an input buffer that is formed from a PMOS differentiated pair of transistors and a first supply voltage. The PMOS differential pair receives a pair of differential inputs, and produces a pair of differential outputs. The structure also includes a level shifter that is coupled to receive the pair of differential outputs from the input buffer to provide gain to the pair of differential outputs to form a gained pair of differential outputs. The level shifter that includes a second supply voltage. The second supply voltage may have a smaller magnitude than the first supply voltage. Finally, the structure includes a CMOS buffer that is coupled to receive the gained pair of differential outputs. The CMOS buffer boosts the gained pair of differential outputs and converts the gained differential pair outputs into a single signal.

摘要翻译： 提供了根据本发明的参考时钟接收器结构。 该结构优选地包括由PMOS差分对晶体管形成的输入缓冲器和第一电源电压。 PMOS差分对接收一对差分输入，并产生一对差分输出。 该结构还包括电平移位器，其被耦合以从输入缓冲器接收一对差分输出，以向该对差分输出提供增益以形成增益的差分输出对。 电平移位器包括第二电源电压。 第二电源电压可以具有比第一电源电压更小的量值。 最后，该结构包括耦合以接收所获得的差分输出对的CMOS缓冲器。 CMOS缓冲器提升了所获得的差分输出对，并将获得的差分对输出转换为单个信号。

公开(公告)号：US5801578A

公开(公告)日：1998-09-01

申请号：US766095

申请日：1996-12-16

申请人： William Bereza

发明人： William Bereza

IPC分类号： H03L7/089 ,  G05F1/10

CPC分类号： H03L7/0896

摘要： A charge pump circuit includes a current mirror circuit of current-sourcing and current-sinking FETs and a current steering circuit of cross coupled differential pairs of FETs. Nominal current flowing in the current-sourcing and current-sinking FETs is set. The current is for charging and discharging a capacitor of an external filter. During charging of the capacitor, the current through the current-sourcing FET is directed to the capacitor and the current through the current-sinking FET is directed from a low impedance voltage source. During discharging of the filter capacitor, the current through the current-sourcing FET is directed to the low impedance voltage source and the current through the current-sinking FET is directed from the capacitor. The current flowing in the current-sourcing and current-sinking FETs is nominally constant, regardless of the tri-state condition, charging or discharging, with the result that power supply noise is reduced. Current change in the power supply rails is reduced when switching from current-sourcing to current-sinking or vice versa. By using cascode FETs in both of the current-sourcing and current-sinking FET circuits, power supply noise rejection is improved.

摘要翻译： 电荷泵电路包括电流源和电流吸收FET的电流镜电路和交叉耦合的差分对FET的电流控制电路。 在电流源和电流吸收FET中流动的标称电流被设定。 电流用于对外部滤波器的电容器进行充电和放电。 在电容器充电期间，通过电流源FET的电流被引导到电容器，并且通过电流吸收FET的电流从低阻抗电压源引导。 在滤波电容器的放电期间，通过电流源FET的电流被引导到低阻抗电压源，并且通过电流吸收FET的电流从电容器引导。 在电流源和电流吸收FET中流动的电流名义上是恒定的，不管三态条件，充电或放电，导致电源噪声降低。 当从电流源切换到电流沉降时反而导致电源轨的电流变化，反之亦然。 通过在电流源和电流吸收FET电路中使用共源共栅FET，提高了电源噪声抑制。

公开(公告)号：US20110156806A1

公开(公告)日：2011-06-30

申请号：US13026859

申请日：2011-02-14

申请人： Haitao Mei ,  Shoujun Wang ,  William Bereza ,  Tad Kwasniewski

发明人： Haitao Mei ,  Shoujun Wang ,  William Bereza ,  Tad Kwasniewski

IPC分类号： G05F1/10

CPC分类号： H03L7/0896

摘要： Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

摘要翻译： 提供了电荷泵电路，对电荷共享和电流失配影响不敏感。 电荷泵电路具有输出节点，在该输出节点处提供电荷泵输出电压。 第一电流源对输出节点充电以增加输出电压，或者第二电流源对输出节点放电以降低输出电压。 电荷泵电路使用单位增益运算放大器电路来防止电荷共享效应在放电和充电操作之间切换时影响输出电压。 低通滤波器用于减少输出节点的反馈噪声。 复制反馈电路防止由第一和第二电流源产生的电流之间的电流失配。 可以使用由可编程元件提供的静态控制信号调整的可编程晶体管来形成第一和第二电流源，以进一步最小化电流失配。

公开(公告)号：US07590207B1

公开(公告)日：2009-09-15

申请号：US11256346

申请日：2005-10-20

申请人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

发明人： Sergey Y Shumarayev ,  Rakesh H Patel ,  Wilson Wong ,  Tim Tri Hoang ,  William Bereza

IPC分类号： H04L7/00

CPC分类号： H03L7/087 ,  H04J3/0688 ,  H04L7/033

摘要： A serial interface for a programmable logic device can be used as a conventional high-speed quad interface, but also allows an individual channel, if not otherwise being used, to be programmably configured as a loop circuit (e.g., a phase-locked loop). This is accomplished by disabling the data loop of clock-data recovery circuitry in the channel, and reconfiguring the reference loop to operate as a loop circuit. In addition, instead of providing a high-speed quad interface having four channels and one or more clock management units (CMUs), a more flexible interface having five or more channels can be provided, and when it is desired to use the interface as a high-speed quad interface, one or more channels can be configured as loop circuits to function as CMUs.

摘要翻译： 用于可编程逻辑器件的串行接口可以用作传统的高速四边形接口，但是也允许单独的通道（如果不另外使用）被可编程地配置为环路电路（例如，锁相环） 。 这是通过禁用通道中的时钟数据恢复电路的数据循环来实现的，并且重新配置参考环路以用作循环电路。 此外，不是提供具有四个通道的高速四边形接口和一个或多个时钟管理单元（CMU），而是可以提供具有五个或更多个通道的更灵活的接口，并且当希望将接口用作 高速四通道接口，一个或多个通道可以配置为循环电路，用作CMU。

公开(公告)号：US07385429B1

公开(公告)日：2008-06-10

申请号：US11142880

申请日：2005-05-31

申请人： Haitao Mei ,  Shoujun Wang ,  William Bereza ,  Tad Kwasniewski

发明人： Haitao Mei ,  Shoujun Wang ,  William Bereza ,  Tad Kwasniewski

IPC分类号： H03L7/06

CPC分类号： H03L7/0896

摘要： Charge pump circuitry is provided that is insensitive to charge sharing and current mismatch effects. The charge pump circuitry has an output node at which a charge pump output voltage is provided. A first current source charges the output node to increase the output voltage or a second current source discharge the output node to decrease the output voltage. The charge pump circuitry uses a unit-gain op-amp circuit to prevent charge sharing effects from affecting the output voltage when switching between discharging and charging operations. A low-pass filter is used to reduce feedback noise on the output node. A replica feedback circuit prevents current mismatch between the currents produced by the first and second current sources. The first and second current sources may be formed using programmable transistors that are adjusted by static control signals provided by programmable elements to further minimize current mismatch.

摘要翻译： 提供了电荷泵电路，对电荷共享和电流失配影响不敏感。 电荷泵电路具有输出节点，在该输出节点处提供电荷泵输出电压。 第一电流源对输出节点充电以增加输出电压，或者第二电流源对输出节点放电以降低输出电压。 电荷泵电路使用单位增益运算放大器电路来防止电荷共享效应在放电和充电操作之间切换时影响输出电压。 低通滤波器用于减少输出节点的反馈噪声。 复制反馈电路防止由第一和第二电流源产生的电流之间的电流失配。 可以使用由可编程元件提供的静态控制信号调整的可编程晶体管来形成第一和第二电流源，以进一步最小化电流失配。

公开(公告)号：US07598779B1

公开(公告)日：2009-10-06

申请号：US10962137

申请日：2004-10-08

申请人： Shoujun Wang ,  Yuming Tao ,  William Bereza ,  Tad Kwasniewski

发明人： Shoujun Wang ,  Yuming Tao ,  William Bereza ,  Tad Kwasniewski

IPC分类号： H03K3/00

CPC分类号： H04L25/0272 ,  H03K19/018528 ,  H03K19/018585

摘要： A dual-mode LVDS/CML transmitter allows a single circuit to operate as either an LVDS transmitter or a CML transmitter. The transmitter mode can be switched by activating or deactivating appropriate circuit elements, and changing the voltage or current produced by appropriate sources or sinks. This flexibility allows a single transmitter to operate well in both AC and DC coupling conditions, and facilitates interoperation with a greater variety of receivers.

摘要翻译： 双模LVDS / CML发射器允许单个电路作为LVDS发射器或CML发射器工作。 可以通过激活或禁用适当的电路元件以及改变由适当的源或汇产生的电压或电流来切换发射器模式。 这种灵活性允许单个发射机在AC和DC耦合条件下运行良好，并且便于与更多种类的接收器的互操作。