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公开(公告)号：US09529671B2
公开(公告)日：2016-12-27
申请号：US14306714
申请日：2014-06-17
Applicant: ARM Limited
Inventor： Vikas Chandra , Robert Campbell Aitken
CPC classification number: G06F11/1076 , G06F11/0727 , G06F11/0751
Abstract: An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.
Abstract translation: 一种装置具有多个存储单元。 奇偶校验发生器被配置为根据存储在多个存储单元中的各个值产生奇偶校验值。 奇偶校验发生器被配置为使得奇偶校验值的确定与存储多个存储单元的数据的读访问无关。 检测器被配置为检测奇偶校验值的值的变化。
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2.发明授权公开(公告)号：US10036774B2
公开(公告)日：2018-07-31
申请号：US14560755
申请日：2014-12-04
Applicant: ARM Limited
Inventor： Gregory Munson Yeric , Vikas Chandra
IPC: G01R31/00 , G01R31/28 , H01L21/66 , H01L25/065
CPC classification number: G01R31/2855 , G01R31/2856 , H01L22/30 , H01L22/34 , H01L25/0655 , H01L25/0657 , H01L2224/48091 , H01L2224/48145 , H01L2224/73204 , H01L2225/06541 , H01L2225/06568 , H01L2225/06589 , H01L2225/06596 , H01L2924/0002 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: An integrated circuit device has at least one environment-hardened die and at least one less-environment-hardened die. Environment-hardened circuitry on the environment-hardened die is more resistant to the degradation when exposed to a predetermined environmental condition than the less-environment-hardened circuitry on the environment-hardened die. The dice are combined using a 3D or 2.5D integrated circuit technology. This is very useful for testing circuits at adverse environmental conditions (e.g. high temperature), or for providing circuits to operate at such conditions.
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3.发明授权公开(公告)号：US09922152B2
公开(公告)日：2018-03-20
申请号：US15078824
申请日：2016-03-23
Applicant: ARM Limited
Inventor： Liangzhen Lai , Vikas Chandra
IPC: G06F17/50
CPC classification number: G06F17/5045
Abstract: A computer-implemented system and method is provided for reducing failure-in-time (FIT) errors associated with one or more sequential devices of a circuit design for a process technology. The method comprises receiving an input data file that includes register transfer level (RTL) data of the circuit design. The RTL data includes the one or more sequential devices. The method further comprises identifying a preferred logic state for each sequential device of the one or more sequential devices. The method further comprises adjusting the one or more sequential devices based on the preferred logic state.
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公开(公告)号：US20170338836A1
公开(公告)日：2017-11-23
申请号：US15157814
申请日：2016-05-18
Applicant: ARM Limited
Inventor： Liangzhen Lai , Vikas Chandra , Gary Dale Carpenter
CPC classification number: H03M13/2906 , H03M13/05 , H03M13/27 , H03M13/2792
Abstract: Various implementations described herein are directed to a memory device. The memory device may include a first interleaving circuit that receives data words and generates a first error correction code based on the received data words. The memory device may include a second interleaving circuit that receives the data words and generates a second error correction code based on the received data words as a complement to the first error correction code. The second interleaving circuit may interleave data bits from multiple different data words and store modified data words based on the multiple different data words.
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公开(公告)号：US09483664B2
公开(公告)日：2016-11-01
申请号：US14486181
申请日：2014-09-15
Applicant: ARM LIMITED
Inventor： Vikas Chandra , Robert Campbell Aitken
CPC classification number: G06F12/1408 , G06F21/72 , G06F21/79 , G06F2212/1052 , G06F2212/402 , G09C1/00 , H04L9/0861 , H04L9/0866 , H04L2209/12
Abstract: Encryption of data within a memory 6 is provided by key generation circuitry 12 which serves to generate a key as a function of the address within the memory 6 being accessed and then encryption circuitry 14 or decryption circuitry 16 which serve respectively to encrypt or decrypt the data as a function of the key that has been generated based upon the address. The encryption and the decryption may be performed using a bitwise XOR operation. The key generation circuitry may have the form of physically unclonable function circuitry, which varies from instance to instance of implementation and that operates to generate the same key for the same address upon both write and read operations within the same instance.
Abstract translation: 存储器6内的数据加密由密钥生成电路12提供，该密钥生成电路12用于生成作为被访问的存储器6内的地址的函数的密钥，然后分别用于加密或解密数据的加密电路14或解密电路16 作为基于地址生成的密钥的函数。 可以使用按位异或运算来执行加密和解密。 密钥生成电路可以具有物理上不可克隆的功能电路的形式，其从实例到实现实例变化，并且在相同的实例中的写入和读取操作两者之间，为同一地址生成相同的密钥。
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Patent Agency Ranking
公开(公告)号：US09214204B2
公开(公告)日：2015-12-15
申请号：US14219498
申请日：2014-03-19
Applicant: ARM LIMITED
Inventor： Vikas Chandra , Peter Beshay
CPC classification number: G11C7/22 , G11C8/08 , G11C11/41 , G11C11/418 , G11C29/021 , G11C29/028 , G11C29/12 , G11C29/24 , G11C2029/1202
Abstract: Apparatus for storing data and a method of adapting a duration of a wordline pulse in an apparatus for storing data are provided. Sensor circuitry comprises a calibrated bitcell which is calibrated to use a duration of wordline pulse which matches a longest wordline pulse required by any bitcell in an array of bitcells for a successful write operation to be carried out. The duration of wordline pulse is signalled to wordline pulse circuitry, which generates a wordline pulse for the array of bitcells with this wordline pulse duration. The sensor circuitry is configured to adapt the wordline pulse duration in dependence on current local conditions in which the apparatus operates to compensate for influence of the current local conditions on the longest wordline pulse required by any bitcell in the array of bitcells.
Abstract translation: 提供了用于存储数据的装置和在用于存储数据的装置中适应字线脉冲的持续时间的方法。 传感器电路包括校准的位单元，其经校准以使用字线脉冲的持续时间，其与位单元阵列中的任何位单元所需的最长字线脉冲匹配，以执行成功的写操作。 字线脉冲的持续时间被发送到字线脉冲电路，该线路脉冲电路利用该字线脉冲持续时间产生用于位单元阵列的字线脉冲。 传感器电路被配置为根据当前本地条件来适应字线脉冲持续时间，其中设备操作以补偿当前局部条件对位单元阵列中任何位单元所需的最长字线脉冲的影响。
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公开(公告)号：US09141338B2
公开(公告)日：2015-09-22
申请号：US13678621
申请日：2012-11-16
Applicant: ARM Limited
Inventor： Sachin Satish Idgunji , Vikas Chandra
IPC: G06F7/58
Abstract: A storage circuit 2 in the form of a master slave latch includes a slave stage 6 serving as a bit storage circuit. The slave stage 6 includes an inverter chain which when operating in a normal mode includes an even number of inverters 10, 12 and when operating in an random number generation mode includes an odd number of inverters 10, 12, 14 and so functions as a free running ring oscillator. When a switch is made back from the random number generation mode to the normal mode, then the oscillation ceases and a stable pseudo random bit value is output from the bit value storage circuit 6.
Abstract translation: 主从锁存器形式的存储电路2包括用作位存储电路的从级6。 从动级6包括一个逆变器链，当在正常模式下操作时包括偶数个反相器10,12，并且当以随机数生成模式操作时，包括奇数个反相器10,12,14等作为自由 运行环形振荡器。 当从随机数生成模式切换回正常模式时，停止振荡，并从位值存储电路6输出稳定的伪随机比特值。
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公开(公告)号：US10366753B2
公开(公告)日：2019-07-30
申请号：US15999694
申请日：2018-08-20
Applicant: Arm Limited
Inventor： Lucian Shifren , Greg Yeric , Saurabh Sinha , Brian Cline , Vikas Chandra
Abstract: Subject matter disclosed herein may relate to programmable fabrics including correlated electron switch devices.
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公开(公告)号：US09891976B2
公开(公告)日：2018-02-13
申请号：US14633062
申请日：2015-02-26
Applicant: ARM Limited
Inventor： Andy Wangkun Chen , Mudit Bhargava , Paul Gilbert Meyer , Vikas Chandra
CPC classification number: G06F11/076 , G06F11/085 , G06F11/1012 , G06F11/1016
Abstract: Various implementations described herein may refer to and may be directed to error detection circuitry for use with memory. In one implementation, an integrated circuit may include a memory array having a plurality of rows of memory cells, where a respective row is configured to store a data word and one or more check bits corresponding to the data word. The integrated circuit may also include inline error detection circuitry coupled to the respective row and configured to generate one or more flag bit values based on a detection of one or more bit errors in the data word stored in the respective row. The integrated circuit may further include error correction circuitry configured to correct the one or more bit errors in the data word stored in the respective row in response to the one or more generated flag bit values.
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公开(公告)号：US09760438B2
公开(公告)日：2017-09-12
申请号：US14306697
申请日：2014-06-17
Applicant: ARM Limited
Inventor： Vikas Chandra , Robert Campbell Aitken
IPC: G06F11/10 , G01R31/3185 , G11C11/419 , G06F1/08 , G01R31/3187 , G06F11/07
CPC classification number: G06F11/1076 , G01R31/3185 , G01R31/318516 , G01R31/318519 , G01R31/318541 , G01R31/318544 , G01R31/318558 , G01R31/318561 , G01R31/3187 , G06F1/08 , G06F11/0727 , G06F11/0751 , G06F11/10 , G06F11/1008 , G06F11/1032 , G06F11/1048 , G11C11/419
Abstract: A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.
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