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公开(公告)号：US20050094431A1
公开(公告)日：2005-05-05
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/06 , G11C16/04 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/00
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译： 非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。 控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。
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2.发明授权Nonvolatile semiconductor memory having a control gate driver transistor whose gate insulator thickness is greater than that of a select gate driver transistor 失效具有栅极绝缘体厚度大于选择栅极驱动晶体管栅极绝缘体厚度的控制栅极驱动晶体管的非易失性半导体存储器公开(公告)号：US07031195B2
公开(公告)日：2006-04-18
申请号：US10948295
申请日：2004-09-24
申请人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
发明人： Atsuhiro Sato , Riichiro Shirota , Kikuko Sugimae , Koji Sakui
IPC分类号： G11C16/08
CPC分类号： G11C16/06 , G11C11/005 , G11C16/0433 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/14 , G11C16/16 , G11C16/26 , H01L27/11521 , H01L27/11546
摘要： A nonvolatile semiconductor memory includes: a memory sub array including a memory cell unit configured with a memory cell transistor and a select transistor connected in series; a control gate line driver including a control gate line driver transistor connected to a control gate line of the memory cell transistor; and a select transistor gate line driver including a select gate line driver transistor connected to a select gate line of the select transistor. A thickness of a gate insulator of the control gate line driver transistor is thicker than that of the select gate line driver transistor.
摘要翻译： 非易失性半导体存储器包括：存储器子阵列，包括配置有存储单元晶体管的存储单元单元和串联连接的选择晶体管; 控制栅极线驱动器，包括连接到存储单元晶体管的控制栅极线的控制栅极线驱动晶体管; 以及选择晶体管栅极线驱动器，其包括连接到选择晶体管的选择栅极线的选择栅极线驱动晶体管。 控制栅极线驱动晶体管的栅极绝缘体的厚度比选择栅线驱动晶体管的厚度厚。
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公开(公告)号：US06667507B2
公开(公告)日：2003-12-23
申请号：US09899155
申请日：2001-07-06
IPC分类号： H01L29788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。
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公开(公告)号：US07361951B2
公开(公告)日：2008-04-22
申请号：US11259142
申请日：2005-10-27
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。
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公开(公告)号：US07045423B2
公开(公告)日：2006-05-16
申请号：US11020314
申请日：2004-12-27
申请人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
发明人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
IPC分类号： H01L21/8247
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.
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6.发明申请公开(公告)号：US20060033151A1
公开(公告)日：2006-02-16
申请号：US11259142
申请日：2005-10-27
IPC分类号： H01L29/788
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
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公开(公告)号：US06977409B2
公开(公告)日：2005-12-20
申请号：US10685599
申请日：2003-10-16
IPC分类号： H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/115 , H01L27/11531 , H01L27/11536
摘要： A semiconductor memory device includes a semiconductor substrate, an element isolation region formed in the semiconductor substrate and including a thick element isolating insulation film, for isolating an element region, a first gate electrode provided on the element region in the semiconductor substrate in self-alignment with the element isolation region, a second gate electrode provided on the first gate electrode with an insulation film interposed therebetween, and a resistance element formed on the element isolation region, the resistance element and the second gate electrode being formed of the same conductive film.
摘要翻译： 半导体存储器件包括半导体衬底，形成在半导体衬底中并包括用于隔离元件区的厚元件隔离绝缘膜的元件隔离区，设置在半导体衬底中的元件区域上的自对准的第一栅电极 在元件隔离区域中，设置在第一栅电极上的绝缘膜的第二栅极电极和形成在元件隔离区域上的电阻元件，电阻元件和第二栅电极由相同的导电膜形成。
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公开(公告)号：US20050104120A1
公开(公告)日：2005-05-19
申请号：US11020314
申请日：2004-12-27
申请人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
发明人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/15 , H01L21/82
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.
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9.发明授权公开(公告)号：US06921960B2
公开(公告)日：2005-07-26
申请号：US09984718
申请日：2001-10-31
IPC分类号： H01L21/768 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/08 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/00
CPC分类号： H01L27/11526 , H01L27/0805 , H01L27/105 , H01L27/11531
摘要： A semiconductor device includes a structure in which a first electrode layer, an inter-electrode insulating film and a second electrode layer are laminated in a main circuit in this order, and includes a capacitor element having a lower electrode formed of the same layer as the first electrode layer, a charge storage layer formed of the same layer as the inter-electrode insulating film, and an upper electrode formed of the second electrode layer. The semiconductor device further includes an opening portion formed in the charge storage layer, the opening portion having a bottom to which the lower electrode is exposed, and a first region electrically connected to the lower electrode via the opening portion and electrically isolated from the upper electrode, the first region being formed of the same layer as the second electrode layer.
摘要翻译： 半导体器件包括其中第一电极层，电极间绝缘膜和第二电极层依次层叠在主电路中的结构，并且包括电容器元件，其具有由与第一电极层相同的层形成的下电极 第一电极层，由与电极间绝缘膜相同的层形成的电荷存储层和由第二电极层形成的上电极。 半导体装置还包括形成在电荷存储层中的开口部分，开口部分具有露出下部电极的底部，以及经由开口部分电连接到下部电极并与上部电极电隔离的第一区域 所述第一区域由与所述第二电极层相同的层形成。
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10.发明授权公开(公告)号：US06853029B2
公开(公告)日：2005-02-08
申请号：US10155086
申请日：2002-05-28
申请人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
发明人： Masayuki Ichige , Yuji Takeuchi , Michiharu Matsui , Atsuhiro Sato , Kikuko Sugimae , Riichiro Shirota
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0483 , H01L27/115 , H01L27/11524 , H01L27/11526 , H01L27/11529
摘要： A semiconductor device includes a semiconductor substrate, source and drain regions, a channel region, a gate insulating film, a charge storage layer, and a control gate electrode. The source and drain regions include first impurities of a first conductivity type. The channel region includes second impurities of a second conductivity type. The gate insulating film includes the second impurities in a region thereof located immediately above at least a portion of the channel region. The charge storage layer is formed on the gate insulating film. The control gate electrode is provided on the charge storage layer. The control gate electrode is formed on the charge storage layer and is electrically connected to the charge storage layer by a connection portion provided on a part of the charge storage layer, which is located immediately above at least a part of the region of the gate insulating film including the second impurities.
摘要翻译： 半导体器件包括半导体衬底，源极和漏极区，沟道区，栅极绝缘膜，电荷存储层和控制栅电极。 源区和漏区包括第一导电类型的第一杂质。 沟道区域包括第二导电类型的第二杂质。 栅极绝缘膜包括位于沟道区域的至少一部分正上方的区域中的第二杂质。 电荷存储层形成在栅极绝缘膜上。 控制栅电极设置在电荷存储层上。 控制栅电极形成在电荷存储层上，并且通过设置在电荷存储层的一部分上的连接部分电连接到电荷存储层，所述连接部位于栅极绝缘区域的至少一部分的正上方 膜包括第二杂质。
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