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公开(公告)号：US4990257A
公开(公告)日：1991-02-05
申请号：US538540
申请日：1990-06-14
CPC分类号： A23L2/085 , B01D61/022
摘要： Provided is a multistage method and apparatus for concentrating a solution by reverse osmosis, comprising the steps and means for: maximizing the concentration of absolute in a solution in a multistage apparatus having only standard capacity pumps, including steps of providing first concentrating means for concentrating a solution to a first concentration, said first concentrating means comprising a least one concentrating unit which positioned upstream with respect to a direction in which a solution to be concentrated flows, and providing second concentrating means for concentrating the solution that has been concentrated by first concentrating means to a second concentration which is higher than said first concentrating means comprising at least one concentrating unit which is positioned downstream with respect to said direction; said concentrating units comprising consisting essentially of respective membrane modules and respective standard capacity pumps, the membrane module of the concentrating unit of said first concentrating means comprising a tight reverse osmosis membrane with a high rejection percentage sufficient to achieve a high concentration of said solution with a high flux density of solvent flowing through the membrane, and the membrane module of the concentrating unit of said second concentrating means comprising a loose reverse osmosis membrane with a lower rejection percentage sufficient to easily achieve a further concentration of said first concentrating means with a high flux density of solution flowing through the membrane.
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公开(公告)号：US5096590A
公开(公告)日：1992-03-17
申请号：US762159
申请日：1991-09-18
CPC分类号： A23L2/085 , B01D61/022
摘要： Provided is a multistage method and apparatus for concentrating a solution by reverse osmosis, comprising the steps and means for: maximizing the concentration of absolute in a solution in a multistage apparatus having only standard capacity pumps, including steps of providing first concentrating means for concentrating a solution to a first concentration, said first concentrating means comprising at least one concentrating unit which positioned upstream with respect to a direction in which a solution to be concentrated flows, and providing second concentrating means for concentrating the solution that has been concentrated by first concentrating means to a second concentration which is higher than said first concentrating means comprising at least one concentrating unit which is positioned downstream with respect to said direction; said concentrating units comprising consisting essentially of respective membrane modules and respective standard capacity pumps, the membrane module of the concentrating unit of said first concentrating means comprising a tight reverse osmosis membrane with a high rejection percentage sufficient to achieve a high concentration of said solution with a high flux density of solvent flowing through the membrane, and the membrane module of the concentrating unit of said second concentrating means comprising a loose reverse osmosis membrane with a lower rejection percentage sufficient to easily achieve a further concentration of said first concentrating means with a high flux density of solution flowing through the membrane.
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公开(公告)号：US08134207B2
公开(公告)日：2012-03-13
申请号：US12028157
申请日：2008-02-08
申请人： Atsuo Watanabe
发明人： Atsuo Watanabe
IPC分类号： H01L29/66 , H01L27/12 , H01L29/786 , H01L21/02 , H01L21/70
CPC分类号： H01L27/1203 , H01L21/76283 , H01L21/76286 , H01L29/0619 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/402 , H01L29/41775 , H01L29/66325 , H01L29/66681 , H01L29/7394 , H01L29/7824
摘要： In a high breakdown voltage semiconductor element among elements integrated together on an SOI substrate in which its rated voltage is shared between an embedded oxide layer and a drain region formed by an element active layer, both high integration and high breakdown voltage are realized while also securing suitability for practical implementation and practical use. The high breakdown voltage is realized without hampering size reduction of the element by forming an electrically floating layer of a conductivity type opposite to that of the drain region at the surface of the drain region. Further, the thickness of the embedded oxide layer is reduced to a level suitable for the practical implementation and practical use by setting the thickness of the element active layer of the SOI substrate at 30 μm or more.
摘要翻译： 在集成在SOI衬底上的元件之间的高耐压电压半导体元件中，其中在由衬底的氧化物层和由元件有源层形成的漏极区域之间共享额定电压，实现高集成度和高击穿电压，同时还确保 适用于实际实施和实际应用。 通过在漏极区的表面形成与漏极区相反的导电类型的电浮置层，实现了高的击穿电压，而不会妨碍元件的尺寸减小。 此外，通过将SOI衬底的元件有源层的厚度设定为30μm以上，将嵌入氧化物层的厚度减小到适于实际实现和实际应用的水平。
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公开(公告)号：US08081781B2
公开(公告)日：2011-12-20
申请号：US11814791
申请日：2006-02-23
申请人： Atsuo Watanabe
发明人： Atsuo Watanabe
IPC分类号： H02B1/00
CPC分类号： H04S5/02 , H03F3/181 , H03F3/217 , H03F3/68 , H03F2200/03
摘要： For achieving an audio reproduction with high sound quality, in a multi-channel A/V amplifier, front speakers are driven with a parallel-drive bi-amplifier arrangement upon stereo reproduction. In the case of the multi-channel reproduction mode, the switching circuit allows an output signal of each channel of the decoder to be sent to speakers via amplifiers for each channel in one-to-one correspondence. On the other hand, in the case of the 2-channel stereo reproduction mode, the switching circuit allows at least two amplifiers among the plurality of amplifiers to be connected in parallel between the output signal for each of the channels L and R of the decoder and the speakers for each of the channels L and R, and also allows the timing of the output signals of the respective amplifiers to be varied.
摘要翻译： 为了实现高音质的音频再现，在多声道A / V放大器中，在立体声再现时，前置扬声器由并行驱动双放大器布置驱动。 在多声道再现模式的情况下，切换电路允许解码器的每个声道的输出信号通过一个对应的每个声道的放大器发送到扬声器。 另一方面，在2声道立体声再现模式的情况下，切换电路允许多个放大器中的至少两个放大器并联连接在解码器的每个通道L和R的输出信号之间 以及每个通道L和R的扬声器，并且还允许各个放大器的输出信号的定时改变。
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公开(公告)号：US20080153216A1
公开(公告)日：2008-06-26
申请号：US12071186
申请日：2008-02-19
申请人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
发明人： Rajesh Kumar , Tsuyoshi Yamamoto , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L21/82
CPC分类号： H01L29/1608 , H01L27/098 , H01L29/0619 , H01L29/66068 , H01L29/8083
摘要： A manufacturing method of a silicon carbide semiconductor device includes the steps of: preparing a semiconductor substrate including a silicon carbide substrate, a drift layer and a first semiconductor layer; forming a plurality of first trenches in a cell portion; forming a gate layer on an inner wall of each first trench by an epitaxial growth method; forming a first insulation film on the surface of the semiconductor substrate; forming a gate electrode on the first insulation film for connecting to the gate layer electrically; forming a source electrode on the first insulation film for connecting to the first semiconductor layer in the cell portion; and forming a drain electrode connected to the silicon carbide substrate electrically.
摘要翻译： 碳化硅半导体器件的制造方法包括以下步骤：制备包括碳化硅衬底，漂移层和第一半导体层的半导体衬底; 在单元部分中形成多个第一沟槽; 通过外延生长法在每个第一沟槽的内壁上形成栅极层; 在所述半导体衬底的表面上形成第一绝缘膜; 在所述第一绝缘膜上形成用于电连接到所述栅极层的栅电极; 在所述第一绝缘膜上形成用于连接到所述单元部分中的所述第一半导体层的源电极; 以及电连接到所述碳化硅衬底的漏电极。
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公开(公告)号：US20070241338A1
公开(公告)日：2007-10-18
申请号：US11783611
申请日：2007-04-10
申请人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
发明人： Tsuyoshi Yamamoto , Toshio Sakakibara , Hiroki Nakamura , Toshiyuki Morishita , Takasumi Ooyanagi , Atsuo Watanabe
IPC分类号： H01L31/0312
CPC分类号： H01L29/1608 , H01L29/0843 , H01L29/1066 , H01L29/8083 , H01L29/872
摘要： A SiC semiconductor device includes: a SiC substrate having a drain layer, a drift layer and a source layer stacked in this order; multiple trenches penetrating the source layer and reaching the drift layer; a gate layer on a sidewall of each trench; an insulation film on the sidewall of each trench covering the gate layer; a source electrode on the source layer; and a diode portion in or under the trench contacting the drift layer to provide a diode. The drift layer between the gate layer on the sidewalls of adjacent two trenches provides a channel region. The diode portion is coupled with the source electrode, and insulated from the gate layer with the insulation film.
摘要翻译： SiC半导体器件包括：具有漏极层，漂移层和源极层的SiC衬底; 多个沟槽穿透源层并到达漂移层; 每个沟槽的侧壁上的栅极层; 覆盖所述栅极层的每个沟槽的侧壁上的绝缘膜; 源极上的源电极; 以及与沟槽接触的沟槽中或下方的二极管部分，以提供二极管。 相邻两个沟槽的侧壁上的栅极层之间的漂移层提供沟道区域。 二极管部分与源电极耦合，并与绝缘膜与栅极层绝缘。
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公开(公告)号：US20070221924A1
公开(公告)日：2007-09-27
申请号：US11802810
申请日：2007-05-25
IPC分类号： H01L29/772
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译： 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。
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公开(公告)号：US07090747B2
公开(公告)日：2006-08-15
申请号：US10415401
申请日：2001-11-07
CPC分类号： D21F3/0227 , C08G18/10 , C08G18/3808 , C08G18/3868 , C08G18/4854 , D21F3/0236 , Y10S162/901 , Y10T428/2457 , Y10T442/2041 , Y10T442/2066 , Y10T442/2098 , Y10T442/30 , C08G18/3814 , C08G18/6685
摘要： A papermaking belt which prevents cracking and inhibits crack growth which includes a reinforcing substrate embedded in a thermosetting polyurethane layer so that the reinforcing substrate and the thermosetting polyurethane layer are integrated with each other and the outer peripheral surface and the inner peripheral surface of the belt are formed by polyurethane layers, the polyurethane layer forming the outer peripheral surface being made of a composition containing a urethane prepolymer having isocyanate groups on its ends and a hardener containing dimethylthiotoluenediamine.
摘要翻译： 一种防止开裂并抑制裂纹生长的造纸带，其包括嵌入热固性聚氨酯层中的增强基材，使得增强基材和热固性聚氨酯层彼此一体化，并且带的外周表面和内周表面是 由聚氨酯层形成，形成外周面的聚氨酯层由含有在其末端具有异氰酸酯基的氨基甲酸酯预聚物和含有二甲基硫代甲苯二胺的固化剂的组合物构成。
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公开(公告)号：US07067878B2
公开(公告)日：2006-06-27
申请号：US09964809
申请日：2001-09-28
申请人： Takasumi Ohyanagi , Atsuo Watanabe
发明人： Takasumi Ohyanagi , Atsuo Watanabe
IPC分类号： H01L31/119
CPC分类号： H01L29/66659 , H01L21/823412 , H01L27/088 , H01L29/0847 , H01L29/1083 , H01L29/7835
摘要： A MOS field effect transistor. A field relaxation layer of a gate overlap structure is disposed in contact with a drain region for the purpose of relaxation of the electric field by increasing a distance between the field relaxation layer and a high-density layer. The electric field relaxation can further be promoted because the equipotential lines are bent by a gate insulation film. A punch-through stopper layer of a gate overlap structure is disposed in contact with a source region for suppressing spreading of a depletion layer toward the source region. The length of a gate electrode can be realized in a miniaturized size.
摘要翻译： MOS场效应晶体管。 为了通过增加场弛豫层和高密度层之间的距离来放电电场，栅极重叠结构的场弛豫层被设置为与漏区接触。 由于等电位线被栅极绝缘膜弯曲，所以可以进一步促进电场弛豫。 栅极重叠结构的穿通停止层设置成与用于抑制耗尽层朝向源极区域扩散的源极区域接触。 可以以小型化的尺寸实现栅电极的长度。
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公开(公告)号：US20060060884A1
公开(公告)日：2006-03-23
申请号：US11138298
申请日：2005-05-27
IPC分类号： H01L29/74
CPC分类号： H01L29/66416 , H01L29/1608 , H01L29/7722 , H01L29/8083
摘要： A silicon carbide semiconductor device such as JFET, SIT and the like is provided for accomplishing a reduction in on-resistance and high-speed switching operations. In the JFET or SIT which turns on/off a current with a depletion layer extending in a channel between a gate region formed along trench grooves, a gate contact layer and a gate electrode, which can be supplied with voltages from the outside, are formed on one surface of a semiconductor substrate or on the bottom of the trench groove. A metal conductor (virtual gate electrode) is formed in ohmic contact with a p++ contact layer of the gate region on the bottom of the trench grooves independently of the gate electrode. The virtual gate electrode is electrically isolated from the gate electrode and an external wire.
摘要翻译： 提供诸如JFET，SIT等的碳化硅半导体器件用于实现导通电阻和高速开关操作的降低。 在JFET或SIT中，形成在沿着沟槽形成的栅极区之间的沟道中延伸的耗尽层的电流，可以从外部供应电压的栅极接触层和栅极电极 在半导体衬底的一个表面上或在沟槽槽的底部。 金属导体（虚拟栅电极）与沟槽沟槽底部的栅极区域的p ++接触层独立于栅电极形成欧姆接触。 虚拟栅电极与栅极电极和外部电线电隔离。
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