公开(公告)号：US20100059822A1

公开(公告)日：2010-03-11

申请号：US12554449

申请日：2009-09-04

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的单个CMOS晶片上制造光子和电子器件。 利用体CMOS工艺和/或利用SOI CMOS工艺的SOI晶片，可以在绝缘体上半导体（SOI）晶片上制造器件。 可以使用双重SOI工艺和/或选择性区域生长工艺来制造不同的厚度。 可以利用一个或多个氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。 集成在CMOS晶片中的二氧化硅或硅锗可以用作蚀刻停止层。

公开(公告)号：US08895413B2

公开(公告)日：2014-11-25

申请号：US13364909

申请日：2012-02-02

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC分类号： H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件，用于光子和电子器件，其结合到每个晶片的至少一部分 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US08877616B2

公开(公告)日：2014-11-04

申请号：US12554449

申请日：2009-09-04

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC分类号： H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on a single CMOS wafer with different silicon layer thicknesses. The devices may be fabricated on a semiconductor-on-insulator (SOI) wafer utilizing a bulk CMOS process and/or on a SOI wafer utilizing a SOI CMOS process. The different thicknesses may be fabricated utilizing a double SOI process and/or a selective area growth process. Cladding layers may be fabricated utilizing one or more oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafer. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions. Silicon dioxide or silicon germanium integrated in the CMOS wafer may be utilized as an etch stop layer.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的单个CMOS晶片上制造光子和电子器件。 利用体CMOS工艺和/或利用SOI CMOS工艺的SOI晶片，可以在绝缘体上半导体（SOI）晶片上制造器件。 可以使用双重SOI工艺和/或选择性区域生长工艺来制造不同的厚度。 可以利用一个或多个氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。 集成在CMOS晶片中的二氧化硅或硅锗可以用作蚀刻停止层。

公开(公告)号：US20120135566A1

公开(公告)日：2012-05-31

申请号：US13364845

申请日：2012-02-02

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

IPC分类号： H01L21/50

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件用于光子和电子器件，其中每个晶片的至少一部分结合在一起 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US09053980B2

公开(公告)日：2015-06-09

申请号：US13364845

申请日：2012-02-02

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  Guckenberger John ,  Attila Mekis

IPC分类号： H01L27/12 ,  H01L21/782 ,  H01L21/84

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices with at least a portion of each of the wafers bonded together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件用于光子和电子器件，其中每个晶片的至少一部分结合在一起 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US08923664B2

公开(公告)日：2014-12-30

申请号：US13156990

申请日：2011-06-09

申请人： Attila Mekis ,  Gianlorenzo Masini

发明人： Attila Mekis ,  Gianlorenzo Masini

IPC分类号： G02B6/12 ,  G02B6/42 ,  G02B6/34 ,  G02B6/00 ,  G02B6/30 ,  G02B6/43 ,  G02B6/38

CPC分类号： G02B6/4239 ,  G02B6/3897 ,  G02B6/43

摘要： A method and system for multi-mode integrated receivers are disclosed and may include receiving an optical signal from an optical fiber coupled to a chip comprising a photonic circuit. The photonic circuit may comprise an optical coupler, one or more multi-mode optical waveguides, and a detector. The received optical signal may be coupled to a plurality of optical modes in the one or more multi-mode optical waveguides, which are communicated to a detector to generate an electrical signal from the communicated modes. The optical coupler may comprise a grating coupler. The chip may comprise a CMOS chip, and the optical fiber may comprise a single-mode or a multi-mode fiber. The detector may comprise a germanium or silicon-germanium photodiode, and/or a waveguide detector. The optical fiber may be coupled to a top surface of the chip and the multi-mode optical waveguides may comprise rib waveguides.

摘要翻译： 公开了一种用于多模式集成接收机的方法和系统，并且可以包括从耦合到包括光子电路的芯片的光纤接收光信号。 光子电路可以包括光耦合器，一个或多个多模光波导和检测器。 接收到的光信号可以耦合到一个或多个多模光波导中的多个光模，其被传送到检测器以从所传送的模式产生电信号。 光耦合器可以包括光栅耦合器。 芯片可以包括CMOS芯片，并且光纤可以包括单模或多模光纤。 检测器可以包括锗或硅锗光电二极管和/或波导检测器。 光纤可以耦合到芯片的顶表面，并且多模光波导可以包括肋波导。

公开(公告)号：US20120132993A1

公开(公告)日：2012-05-31

申请号：US13364909

申请日：2012-02-02

申请人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

发明人： Thierry Pinguet ,  Steffen Gloeckner ,  Peter De Dobbelaere ,  Sherif Abdalla ,  Daniel Kucharski ,  Gianlorenzo Masini ,  Kosei Yokoyama ,  John Guckenberger ,  Attila Mekis

IPC分类号： H01L27/12 ,  H01L21/782

CPC分类号： H04B10/2575 ,  H01L21/84 ,  H01L27/1203 ,  H04B10/40

摘要： Methods and systems for monolithic integration of photonics and electronics in CMOS processes are disclosed and may include fabricating photonic and electronic devices on two CMOS wafers with different silicon layer thicknesses for the photonic and electronic devices bonded to at least a portion of each of the wafers together, where a first of the CMOS wafers includes the photonic devices and a second of the CMOS wafers includes the electronic devices. The electrical devices may be coupled to optical devices utilizing through-silicon vias. The different thicknesses may be fabricated utilizing a selective area growth process. Cladding layers may be fabricated utilizing oxygen implants and/or utilizing CMOS trench oxide on the CMOS wafers. Silicon may be deposited on the CMOS trench oxide utilizing epitaxial lateral overgrowth. Cladding layers may be fabricated utilizing selective backside etching. Reflective surfaces may be fabricated by depositing metal on the selectively etched regions.

摘要翻译： 公开了用于在CMOS工艺中单片集成光子学和电子学的方法和系统，并且可以包括在具有不同硅层厚度的两个CMOS晶片上制造光子和电子器件，用于光子和电子器件，其结合到每个晶片的至少一部分 其中第一CMOS晶片包括光子器件，并且第二CMOS晶片包括电子器件。 电子器件可以利用穿硅通孔耦合到光学器件。 可以使用选择性区域生长过程来制造不同的厚度。 可以使用氧注入和/或在CMOS晶片上利用CMOS沟槽氧化物来制造覆层。 硅可以利用外延横向过度生长沉积在CMOS沟槽氧化物上。 可以利用选择性背面蚀刻来制造包覆层。 可以通过在选择性蚀刻的区域上沉积金属来制造反射表面。

公开(公告)号：US20190215079A1

公开(公告)日：2019-07-11

申请号：US16353591

申请日：2019-03-14

申请人： Peter De Dobbelaere ,  Attila Mekis ,  Gianlorenzo Masini

发明人： Peter De Dobbelaere ,  Attila Mekis ,  Gianlorenzo Masini

IPC分类号： H04B10/80 ,  G02B6/34 ,  G02B6/122 ,  G02B6/42 ,  G02B6/43

CPC分类号： H04B10/801 ,  G02B6/1228 ,  G02B6/34 ,  G02B6/4279 ,  G02B6/428 ,  G02B6/4292 ,  G02B6/43

摘要： Methods and systems for large silicon photonic interposers by stitching are disclosed and may include, in an optical communication system including a silicon photonic interposer, where the interposer includes a plurality of reticle sections: communicating an optical signal between two of the plurality of reticle sections utilizing a waveguide. The waveguide may include a taper region at a boundary between the two reticle sections, the taper region expanding an optical mode of the communicated optical signal prior to the boundary and narrowing the optical mode after the boundary. A continuous wave (CW) optical signal may be received in a first of the reticle sections from an optical source external to the interposer. The CW optical signal may be received in the interposer from an optical source assembly coupled to a grating coupler in the first of the reticle sections in the silicon photonic interposer.

公开(公告)号：US20190196230A1

公开(公告)日：2019-06-27

申请号：US16293233

申请日：2019-03-05

申请人： Attila Mekis ,  Adithyaram Narasimha ,  Jeremy Witzens

发明人： Attila Mekis ,  Adithyaram Narasimha ,  Jeremy Witzens

IPC分类号： G02F1/01 ,  G02B6/42 ,  G02B6/125 ,  G02B6/27 ,  G02B6/34 ,  G02B6/293 ,  G02B6/126 ,  G02F1/313

CPC分类号： G02F1/0136 ,  G02B6/125 ,  G02B6/126 ,  G02B6/2726 ,  G02B6/2773 ,  G02B6/29344 ,  G02B6/34 ,  G02B6/4286 ,  G02B2006/12142 ,  G02F1/011 ,  G02F1/313

摘要： A system for integrated power combiners is disclosed and may include receiving optical signals in input optical waveguides and phase-modulating the signals to configure a phase offset between signals received at a first optical coupler, where the first optical coupler may generate output signals having substantially equal optical powers. Output signals of the first optical coupler may be phase-modulated to configure a phase offset between signals received at a second optical coupler, which may generate an output signal having an optical power of essentially zero and a second output signal having a maximized optical power. Optical signals received by the input optical waveguides may be generated utilizing a polarization-splitting grating coupler to enable polarization-insensitive combining of optical signals. Optical power may be monitored using optical detectors. The monitoring of optical power may be used to determine a desired phase offset between the signals received at the first optical coupler.

公开(公告)号：US20120314997A1

公开(公告)日：2012-12-13

申请号：US13590821

申请日：2012-08-21

申请人： Thierry Pinguet ,  Attila Mekis ,  Steffen Gloeckner

发明人： Thierry Pinguet ,  Attila Mekis ,  Steffen Gloeckner

IPC分类号： G02B6/34

CPC分类号： G02B6/124 ,  G01J1/02 ,  G01J1/0425 ,  G02B6/12004 ,  G02B6/30 ,  G02B6/34 ,  G02B6/4208 ,  G02B2006/12038 ,  G02B2006/12061 ,  G02B2006/12104 ,  G02B2006/12157

摘要： A method and system for coupling optical signals into silicon optoelectronic chips are disclosed and may include coupling one or more optical signals into a back surface of one or more of a plurality of CMOS photonic chips comprising photonic, electronic, and optoelectronic devices. The devices may be integrated in a front surface of the chips and optical couplers may receive the optical signals in the front surface of the chips. The optical signals may be coupled into the back surface of the chips via optical fibers and/or optical source assemblies. The optical signals may be coupled to the optical couplers via a light path etched in the chips, which may be refilled with silicon dioxide. The chips may be flip-chip bonded to a packaging substrate. Optical signals may be reflected back to the optical couplers via metal reflectors, which may be integrated in dielectric layers on the chips.

摘要翻译： 公开了一种用于将光信号耦合到硅光电子芯片的方法和系统，并且可以包括将一个或多个光信号耦合到包括光子，电子和光电器件的多个CMOS光子芯片中的一个或多个的后表面中。 这些器件可以集成在芯片的前表面中，并且光耦合器可以接收芯片前表面中的光信号。 光信号可以经由光纤和/或光源组件耦合到芯片的后表面中。 光信号可以经由在芯片中蚀刻的光路耦合到光耦合器，其可以用二氧化硅再填充。 芯片可以倒装芯片结合到封装基板。 光信号可以经由金属反射器反射回到光耦合器，金属反射器可以集成在芯片上的电介质层中。