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公开(公告)号：US11616187B2
公开(公告)日：2023-03-28
申请号：US17168443
申请日：2021-02-05
申请人： Aurelius L. Graninger , Joel D. Strand , Micah John Atman Stoutimore , Zachary Kyle Keane , Jeffrey David Hartman , Justin C. Hackley
发明人： Aurelius L. Graninger , Joel D. Strand , Micah John Atman Stoutimore , Zachary Kyle Keane , Jeffrey David Hartman , Justin C. Hackley
IPC分类号： H01L39/02 , G01R31/28 , H01L21/66 , H01L23/00 , H01L25/065 , H01L27/18 , H01L39/08 , H01L39/10 , H01L39/12 , H01L39/06 , H01L39/22
摘要： Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.
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公开(公告)号：US10950778B2
公开(公告)日：2021-03-16
申请号：US16241661
申请日：2019-01-07
申请人： Aurelius L. Graninger , Joel D. Strand , Micah John Atman Stoutimore , Zachary Kyle Keane , Jeffrey David Hartman , Justin C. Hackley
发明人： Aurelius L. Graninger , Joel D. Strand , Micah John Atman Stoutimore , Zachary Kyle Keane , Jeffrey David Hartman , Justin C. Hackley
IPC分类号： H01L29/06 , H01L39/02 , G01R31/28 , H01L21/66 , H01L23/00 , H01L25/065 , H01L27/18 , H01L39/08 , H01L39/10 , H01L39/12 , H01L39/06 , H01L39/22
摘要： Test structures and methods for superconducting bump bond electrical characterization are used to verify the superconductivity of bump bonds that electrically connect two superconducting integrated circuit chips fabricated using a flip-chip process, and can also ascertain the self-inductance of bump bond(s) between chips. The structures and methods leverage a behavioral property of superconducting DC SQUIDs to modulate a critical current upon injection of magnetic flux in the SQUID loop, which behavior is not present when the SQUID is not superconducting, by including bump bond(s) within the loop, which loop is split among chips. The sensitivity of the bump bond superconductivity verification is therefore effectively perfect, independent of any multi-milliohm noise floor that may exist in measurement equipment.
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公开(公告)号：US10651233B2
公开(公告)日：2020-05-12
申请号：US16107321
申请日：2018-08-21
摘要： A superconducting structure includes a first superconducting device having a plurality of first superconducting contact pads disposed on a top side of a first superconducting device, a second superconducting device having a plurality of second superconducting contact pads disposed on a bottom side of a second superconducting device, and a plurality of superconducting bump structures with a given bump structure coupling respective superconducting contact pads of the plurality of first superconducting contact pads and the second plurality of superconducting pads to one another to bond the first superconducting device to the second superconducting device. Each superconducting bump structure includes a first under bump metallization (UBM) layer disposed on the top surface of a given superconducting contact pad, a second UBM layer disposed on the top surface of a given superconducting contact pads, and a superconducting metal layer coupling the first UBM layer to the second UBM layer.
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公开(公告)号：US09780465B1
公开(公告)日：2017-10-03
申请号：US15270816
申请日：2016-09-20
CPC分类号： H01R12/722 , H01R12/737 , H05K1/14 , H05K3/366 , H05K3/403 , H05K3/4617 , H05K3/4682 , H05K2201/046 , H05K2201/09154 , H05K2201/0919 , H05K2201/10189 , H05K2203/0228
摘要： An angled circuit board connector includes a unitary connector block having first and second board-contacting faces. The first and second board-contacting faces are arranged relative to each other at an operative angle. The connector block includes a block body. The first and second board-contacting faces face outward from the block body. A first connector port is located on the first board-contacting face. A second connector port is located on the second board-contacting face. A connector trace extends through at least a portion of the block body between the first and second board-contacting faces. The connector trace electrically connects the first and second connector ports.
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公开(公告)号：US10681812B2
公开(公告)日：2020-06-09
申请号：US16439415
申请日：2019-06-12
摘要： A flexible connector includes a unitary connector block having first and second board-facing areas. The first and second board-facing areas are longitudinally spaced from each other on a chosen surface of the connector block. The connector block includes a block body transversely separating the chosen surface from an opposing surface oppositely facing from the chosen surface. The connector block includes a flexible connector bridge longitudinally interposed between the first and second board-facing areas. A first connector port is located within the first board-facing area. A second connector port is located within the second board-facing area. A connector trace extends through at least a portion of the block body between the first and second board-facing areas. The connector trace electrically connects the first and second connector ports. Methods of making and using the flexible connector are also included.
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公开(公告)号：US10340568B2
公开(公告)日：2019-07-02
申请号：US16008848
申请日：2018-06-14
摘要： An apparatus includes a top conductive layer of on an integrated circuit waveguide filter and a bottom conductive layer. The top and bottom conductive layers are coupled via a plurality of couplers that form an outline of the waveguide filter. A dielectric substrate layer is disposed between the top conductive layer and the bottom conductive layer of the integrated circuit waveguide filter. The dielectric substrate layer has a relative permittivity, εr that affects the tuning of the integrated circuit waveguide filter. At least one tunable via includes a tunable material disposed within the dielectric substrate layer and is coupled to a set of electrodes. The set of electrodes enable a voltage to be applied to the tunable material within the tunable via to change the relative permittivity of the dielectric substrate layer and to enable tuning the frequency characteristics of the integrated circuit waveguide filter.
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公开(公告)号：US10027005B2
公开(公告)日：2018-07-17
申请号：US15010987
申请日：2016-01-29
摘要： An apparatus includes a top conductive layer of on an integrated circuit waveguide filter and a bottom conductive layer. The top and bottom conductive layers are coupled via a plurality of couplers that form an outline of the waveguide filter. A dielectric substrate layer is disposed between the top conductive layer and the bottom conductive layer of the integrated circuit waveguide filter. The dielectric substrate layer has a relative permittivity, εr that affects the tuning of the integrated circuit waveguide filter. At least one tunable via includes a tunable material disposed within the dielectric substrate layer and is coupled to a set of electrodes. The set of electrodes enable a voltage to be applied to the tunable material within the tunable via to change the relative permittivity of the dielectric substrate layer and to enable tuning the frequency characteristics of the integrated circuit waveguide filter.
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