公开(公告)号：US20180366642A1

公开(公告)日：2018-12-20

申请号：US16112173

申请日：2018-08-24

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Dong Ha Jung ,  Jing Zhang ,  Bing K. Yen

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/224 ,  H01L43/08

摘要： The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a selector film stack on a substrate; depositing a magnetic memory element film stack on top of the selector film stack; etching the magnetic memory element film stack with an etch mask formed thereon to remove at least an insulating tunnel junction layer in the magnetic memory element film stack not covered by the etch mask, thereby forming a magnetic memory element pillar; depositing a first conforming dielectric layer over the magnetic memory element pillar, including a sidewall thereof, and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the insulating tunnel junction layer of the magnetic memory element pillar; and etching the selector film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

公开(公告)号：US09123575B1

公开(公告)日：2015-09-01

申请号：US14336640

申请日：2014-07-21

申请人： Avalanche Technology, Inc.

发明人： Kimihiro Satoh ,  Bing K Yen ,  Dong Ha Jung ,  Yiming Huai

IPC分类号： H01L27/00 ,  H01L27/108 ,  H01L27/06 ,  H01L27/24 ,  H01L45/00 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along the first direction with each of the multiple contact regions including a first row and a second row of the first level contacts extending along a second direction; a first and second plurality of second level contacts formed on top of the first level contacts with the second plurality of second level contacts having elongated shape extending into the vacant regions adjacent thereto; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively, thereby permitting the memory elements to have greater center-to-center distance between two closest neighbors than the first level contacts.

摘要翻译： 本发明涉及一种半导体存储器件，其包括多个第一电平触点，每个第一电平触点沿阵列排列，每第三行沿着第一方向空置，从而形成多个接触区域，该接触区域沿多个空白区域沿第一方向分开， 包括沿第二方向延伸的第一级触点的第一行和第二行的接触区域; 形成在第一级顶部上的第一和第二多个第二级触点与第二多个第二级触点具有延伸到与其相邻的空缺区域中的细长形状; 以及分别形成在第一和第二多个第二电平触点的顶部上的第一和第二多个存储元件，从而允许存储元件在与第一电平触点之间的两个最接近的邻近之间具有更大的中心到中心距离。

公开(公告)号：US10217934B2

公开(公告)日：2019-02-26

申请号：US16112173

申请日：2018-08-24

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Dong Ha Jung ,  Jing Zhang ,  Bing K. Yen

IPC分类号： H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08

摘要： The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a selector film stack on a substrate; depositing a magnetic memory element film stack on top of the selector film stack; etching the magnetic memory element film stack with an etch mask formed thereon to remove at least an insulating tunnel junction layer in the magnetic memory element film stack not covered by the etch mask, thereby forming a magnetic memory element pillar; depositing a first conforming dielectric layer over the magnetic memory element pillar, including a sidewall thereof, and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the insulating tunnel junction layer of the magnetic memory element pillar; and etching the selector film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

公开(公告)号：US20150104882A1

公开(公告)日：2015-04-16

申请号：US14051327

申请日：2013-10-10

申请人： Avalanche Technology Inc.

发明人： Dong Ha Jung ,  Kimihiro Satoh ,  Jing Zhang ,  Yuchen Zhou ,  Yiming Huai

IPC分类号： H01L43/12

CPC分类号： H01L43/12 ,  H01L27/222

摘要： Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer.

摘要翻译： 描述了本发明的实施例，使用可以是双层膜的薄金属硬掩模，以增加用于MTJ侧壁清洁的入射IBE角度，而不会损失后续互连过程的工艺余量。 图案化的金属硬掩模垫还用作MTJ电池的顶部电极。 当硬掩模材料充当CMP塞子而没有显着的厚度损失时，可以使用薄金属硬掩模。 在第一实施例中，单层硬掩模优选为钌。 在第二实施例中，双层硬掩模的下层优选为钌。 晶片优选在IBE工艺期间旋转以进行均匀蚀刻。 在硬掩模蚀刻工艺期间，优选使用硬掩模下面的覆盖层作为蚀刻停止层，以便不损坏或蚀刻通过上磁性层。

公开(公告)号：US08962349B1

公开(公告)日：2015-02-24

申请号：US14089209

申请日：2013-11-25

申请人： Avalanche Technology Inc.

发明人： Benjamin Chen ,  Kimihiro Satoh ,  Jing Zhang ,  Dong Ha Jung

IPC分类号： H01L43/02 ,  H01L43/12

CPC分类号： H01L43/12

摘要： The present invention is directed to a method for fabricating a magnetic tunnel junction (MTJ) memory element. The method comprises the steps of providing a substrate having a contact dielectric layer, a bottom dielectric layer, a bottom electrode layer, an etch stop layer, an MTJ layer stack, and a top electrode layer sequentially formed thereon; etching the top electrode layer with a first mask thereon to form a top electrode; etching the MTJ layer stack with the top electrode thereon to form a patterned MTJ; encapsulating the patterned MTJ with a passivation layer; depositing a top dielectric layer on top of the passivation layer and planarizing the same layer; forming a second mask on the top dielectric layer; and etching the bottom electrode layer, the etch stop layer, the passivation layer, and the top dielectric layer with the second mask thereon to form a bottom electrode.

摘要翻译： 本发明涉及一种制造磁性隧道结（MTJ）存储元件的方法。 该方法包括以下步骤：提供具有接触电介质层，底部电介质层，底部电极层，蚀刻停止层，MTJ层叠层和顺序地形成在其上的顶部电极层的衬底; 用其上的第一掩模蚀刻顶部电极层以形成顶部电极; 用顶部电极在其上蚀刻MTJ层叠层以形成图案化的MTJ; 用钝化层封装图案化的MTJ; 在顶部介电层上沉积钝化层，并平坦化同一层; 在所述顶部介电层上形成第二掩模; 并在其上蚀刻底部电极层，蚀刻停止层，钝化层和顶部电介质层，以形成底部电极。

公开(公告)号：US20150014801A1

公开(公告)日：2015-01-15

申请号：US14501553

申请日：2014-09-30

申请人： Avalanche Technology, Inc.

发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Parviz Keshtbod ,  Ebrahim Abedifard ,  Yiming Huai ,  Jing Zhang

IPC分类号： H01L43/02

CPC分类号： H01L43/02 ,  H01L27/222 ,  H01L43/12

摘要： Methods and structures are described to reduce metallic redeposition material in the memory cells, such as MTJ cells, during pillar etching. One embodiment forms metal studs on top of the landing pads in a dielectric layer that otherwise covers the exposed metal surfaces on the wafer. Another embodiment patterns the MTJ and bottom electrode separately. The bottom electrode mask then covers metal under the bottom electrode. Another embodiment divides the pillar etching process into two phases. The first phase etches down to the lower magnetic layer, then the sidewalls of the barrier layer are covered with a dielectric material which is then vertically etched. The second phase of the etching then patterns the remaining layers. Another embodiment uses a hard mask above the top electrode to etch the MTJ pillar until near the end point of the bottom electrode, deposits a dielectric, then vertically etches the remaining bottom electrode.

摘要翻译： 描述了方法和结构以在柱蚀刻期间减少存储器单元（例如MTJ电池）中的金属沉积材料。 一个实施例在位于晶片上暴露的金属表面的电介质层中的着陆焊盘的顶部上形成金属螺柱。 另一个实施例分别对MTJ和底部电极进行图案化。 底部电极掩模然后覆盖底部电极下面的金属。 另一实施例将柱蚀刻工艺分为两个阶段。 第一阶段蚀刻到较低的磁性层，然后阻挡层的侧壁被电介质材料覆盖，然后将其垂直蚀刻。 蚀刻的第二阶段然后对剩余的层进行图案化。 另一个实施例使用顶部电极上方的硬掩模来蚀刻MTJ柱直到靠近底部电极的端点，沉积电介质，然后垂直蚀刻剩余的底部电极。

公开(公告)号：US10177308B2

公开(公告)日：2019-01-08

申请号：US15618510

申请日：2017-06-09

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Dong Ha Jung ,  Jing Zhang ,  Bing K. Yen

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

摘要： The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a magnetic memory element film stack on a substrate; depositing a selector film stack on top of the magnetic memory element film stack; etching the selector film stack with an etch mask formed thereon to remove at least a switching layer in the selector film stack not covered by the etch mask, thereby forming a selector pillar; depositing a first conforming dielectric layer over the selector pillar and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the switching layer of the selector pillar; and etching the magnetic memory element film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

公开(公告)号：US20180358547A1

公开(公告)日：2018-12-13

申请号：US15618510

申请日：2017-06-09

申请人： Avalanche Technology, Inc.

发明人： Hongxin Yang ,  Dong Ha Jung ,  Jing Zhang ,  Bing K. Yen

IPC分类号： H01L43/12 ,  H01L43/08 ,  H01L27/22 ,  G11C11/16

CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/224 ,  H01L43/08

摘要： The present invention is directed to a method for manufacturing a memory cell that includes a magnetic memory element electrically connected to a two-terminal selector. The method includes the steps of depositing a magnetic memory element film stack on a substrate; depositing a selector film stack on top of the magnetic memory element film stack; etching the selector film stack with an etch mask formed thereon to remove at least a switching layer in the selector film stack not covered by the etch mask, thereby forming a selector pillar; depositing a first conforming dielectric layer over the selector pillar and surrounding surface; etching a portion of the first conforming dielectric layer covering the surrounding surface to form a first protective sleeve around at least the switching layer of the selector pillar; and etching the magnetic memory element film stack using the etch mask and the first protective sleeve as a composite mask to form a memory cell pillar.

公开(公告)号：US09166154B2

公开(公告)日：2015-10-20

申请号：US14096016

申请日：2013-12-04

申请人： Avalanche Technology Inc.

发明人： Kimihiro Satoh ,  Dong Ha Jung ,  Jing Zhang ,  Benjamin Chen ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Yuchen Zhou

IPC分类号： H01L29/04 ,  H01L43/12

CPC分类号： H01L43/12

摘要： Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

摘要翻译： 描述了使用离子束蚀刻（IBE）对MRAM单元记忆元件的制造方法。 在本发明的实施例中，使用诸如RIE或磁化感应耦合等离子体（MICP）的反应蚀刻用一个掩模来蚀刻顶部电极和MTJ主体以提高选择性，然后使用如在各种替代实施例中所规定的IBE蚀刻底部电极 包括在IBE之前沉积的入射角，晶片旋转速率曲线和可选的钝化层的选择。 根据本发明的IBE通过使用由第一蚀刻阶段产生的层堆叠作为掩模来蚀刻底部电极而不需要附加掩模。 这使得底部电极与MTJ自对准。 IBE还实现了MTJ侧墙清洁，无需额外的步骤。

公开(公告)号：US09070869B2

公开(公告)日：2015-06-30

申请号：US14051327

申请日：2013-10-10

申请人： Avalanche Technology Inc.

发明人： Dong Ha Jung ,  Kimihiro Satoh ,  Jing Zhang ,  Yuchen Zhou ,  Yiming Huai

IPC分类号： H01L21/00 ,  H01L43/12 ,  H01L27/22

CPC分类号： H01L43/12 ,  H01L27/222

摘要： Embodiments of the invention are described that use a thin metallic hard mask, which can be a bi-layer film, to increase the incident IBE angle for MTJ sidewall cleaning without losing the process margin for the subsequent interconnection process. The patterned metallic hard mask pads also serve as the top electrode for the MTJ cells. Using a thin metallic hard mask is possible when the hard mask material acts as a CMP stopper without substantial loss of thickness. In the first embodiment, the single layer hard mask is preferably ruthenium. In the second embodiment, the lower layer of the bi-layer hard mask is preferably ruthenium. The wafer is preferably rotated during the IBE process for uniform etching. A capping layer under the hard mask is preferably used as the etch stopper during hard mask etch process in order not to damage or etch through the upper magnetic layer.

摘要翻译： 描述了本发明的实施例，使用可以是双层膜的薄金属硬掩模，以增加用于MTJ侧壁清洁的入射IBE角度，而不会损失后续互连过程的工艺余量。 图案化的金属硬掩模垫还用作MTJ电池的顶部电极。 当硬掩模材料充当CMP塞子而没有显着的厚度损失时，可以使用薄金属硬掩模。 在第一实施例中，单层硬掩模优选为钌。 在第二实施例中，双层硬掩模的下层优选为钌。 晶片优选在IBE工艺期间旋转以进行均匀蚀刻。 在硬掩模蚀刻工艺期间，优选使用硬掩模下面的覆盖层作为蚀刻停止层，以便不损坏或蚀刻通过上磁性层。