公开(公告)号：US11127787B2

公开(公告)日：2021-09-21

申请号：US16793349

申请日：2020-02-18

Applicant: Avalanche Technology, Inc.

Inventor： Hongxin Yang ,  Bing K. Yen ,  Jing Zhang

IPC: H01L27/22 ,  H01L43/10 ,  H01L43/08 ,  G11C11/16 ,  G11C16/10 ,  H01L45/00

Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes at least one conductor layer interleaved with insulating layers.

公开(公告)号：US10559624B2

公开(公告)日：2020-02-11

申请号：US15438631

申请日：2017-02-21

Applicant: Avalanche Technology, Inc.

Inventor： Hongxin Yang ,  Xiaojie Hao ,  Jing Zhang ,  Xiaobin Wang ,  Bing K. Yen

IPC: H01L27/22 ,  H01L43/08

Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element, which has a low resistance state and a high resistance state, and a two-terminal selector coupled to the MTJ memory element in series. The MTJ memory element includes a magnetic free layer and a magnetic reference layer with an insulating tunnel junction layer interposed therebetween. The two-terminal selector has an insulative state and a conductive state. The two-terminal selector in the conductive state has substantially lower resistance when switching the MTJ memory element from the low to high resistance state than from the high to low resistance state. The voltages applied to the memory cell to respectively switch the MTJ memory element from the low to high resistance state and from the high to low resistance state may be substantially same.

公开(公告)号：US20180240845A1

公开(公告)日：2018-08-23

申请号：US15863825

申请日：2018-01-05

Applicant: Avalanche Technology, Inc.

Inventor： Hongxin Yang ,  Bing K. Yen ,  Jing Zhang

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/10

CPC classification number: H01L27/224 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C16/10 ,  H01L43/08 ,  H01L43/10 ,  H01L45/085

Abstract: The present invention is directed to a memory cell that includes a magnetic tunnel junction (MTJ) memory element and a two-terminal selector element coupled in series. The MTJ memory element includes a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween. The magnetic reference layer structure includes one or more magnetic reference layers having a first invariable magnetization direction substantially perpendicular to layer planes thereof. The two-terminal selector element includes a first inert electrode and a second inert electrode with a volatile switching layer interposed therebetween; a first active electrode formed adjacent to the first inert electrode; and a second active electrode formed adjacent to the second inert electrode. The volatile switching layer includes a plurality of metal-rich particles or clusters embedded in a matrix or at least one conductor layer interleaved with insulating layers.

公开(公告)号：US09419210B2

公开(公告)日：2016-08-16

申请号：US15072254

申请日：2016-03-16

Applicant: Avalanche Technology, Inc.

Inventor： Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Yuchen Zhou ,  Roger Klas Malmhall

IPC: G11C16/00 ,  H01L43/10 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

CPC classification number: H01L43/10 ,  B82Y40/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01L27/228 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08

Abstract: The present invention is directed to a spin transfer torque magnetic random access memory (STTMRAM) element comprising a composite free layer including one or more stacks of a bilayer unit that comprises an insulator layer and a magnetic layer with the magnetic layer having a variable magnetization direction substantially perpendicular to a layer plane thereof; a magnetic pinned layer having a first fixed magnetization direction substantially perpendicular to a layer plane thereof; a tunnel barrier layer formed between the composite free layer and the magnetic pinned layer; and a magnetic fixed layer coupled to the magnetic pinned layer through an anti-ferromagnetic coupling layer. The magnetic fixed layer has a second fixed magnetization direction that is substantially perpendicular to a layer plane thereof and is substantially opposite to the first fixed magnetization direction.

Abstract translation: 本发明涉及一种自旋转移转矩磁随机存取存储器（STTMRAM）元件，它包括一个复合自由层，该复合自由层包括一个或多个双层单元堆叠，所述双层单元包括绝缘体层和磁性层，该磁性层具有可变的磁化方向 基本上垂直于其层平面; 磁性钉扎层，其具有基本上垂直于其层平面的第一固定磁化方向; 形成在复合自由层和磁性被钉扎层之间的隧道势垒层; 以及通过反铁磁耦合层耦合到磁性被钉扎层的磁性固定层。 磁性固定层具有基本上垂直于其层平面并基本上与第一固定磁化方向相反的第二固定磁化方向。

公开(公告)号：US20160197269A1

公开(公告)日：2016-07-07

申请号：US15072254

申请日：2016-03-16

Applicant: Avalanche Technology, Inc.

Inventor： Yiming Huai ,  Jing Zhang ,  Rajiv Yadav Ranjan ,  Yuchen Zhou ,  Roger Klas Malmhall

IPC: H01L43/10 ,  H01L43/02 ,  G11C11/16 ,  H01L43/08

CPC classification number: H01L43/10 ,  B82Y40/00 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01L27/228 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08

Abstract: The present invention is directed to a spin transfer torque magnetic random access memory (STTMRAM) element comprising a composite free layer including one or more stacks of a bilayer unit that comprises an insulator layer and a magnetic layer with the magnetic layer having a variable magnetization direction substantially perpendicular to a layer plane thereof; a magnetic pinned layer having a first fixed magnetization direction substantially perpendicular to a layer plane thereof; a tunnel barrier layer formed between the composite free layer and the magnetic pinned layer; and a magnetic fixed layer coupled to the magnetic pinned layer through an anti-ferromagnetic coupling layer. The magnetic fixed layer has a second fixed magnetization direction that is substantially perpendicular to a layer plane thereof and is substantially opposite to the first fixed magnetization direction.

Abstract translation: 本发明涉及一种自旋转移转矩磁随机存取存储器（STTMRAM）元件，它包括一个复合自由层，该复合自由层包括一个或多个双层单元叠层，该双层单元包括绝缘体层和磁性层，该磁性层具有可变的磁化方向 基本上垂直于其层平面; 磁性钉扎层，其具有基本上垂直于其层平面的第一固定磁化方向; 形成在复合自由层和磁性被钉扎层之间的隧道势垒层; 以及通过反铁磁耦合层耦合到磁性被钉扎层的磁性固定层。 磁性固定层具有基本上垂直于其层平面并基本上与第一固定磁化方向相反的第二固定磁化方向。

公开(公告)号：US09070692B2

公开(公告)日：2015-06-30

申请号：US13740180

申请日：2013-01-12

Applicant: Avalanche Technology Inc.

Inventor： Yuchen Zhou ,  Bernardo Sardinha ,  Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Roger Klas Malmhall ,  Zihui Wang ,  Yiming Huai ,  Jing Zhang

IPC: H01L23/552 ,  H01L23/00

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Chip packages are described with soft-magnetic shields that are included inside or attached externally to the package containing a MRAM chip. In one group of embodiments a single shield with vias for bonding wires is affixed to the surface of the MRAM chip having the contact pads. The limitation of shield to chip distance due to bonding wire is eliminated by VIA holes according to the invention which achieves minimal spacing between the shield and chip. A second shield without vias can be positioned on the opposite side of the chip from the first shield. In one group of embodiments a hardened ferro-fluid shield can be the only shield or the structure can include a shield with or without vias. One group of embodiments includes an external shield with vias for solder access to the package contact pads affixed to the outer surface of the package.

Abstract translation: 使用包含在包含MRAM芯片的封装内部或外部附加的软磁屏蔽来描述芯片封装。 在一组实施例中，具有用于接合线的通孔的单个屏蔽件固定到具有接触垫的MRAM芯片的表面上。 通过根据本发明的VIA孔消除了由于接合线导致的屏蔽到芯片距离的限制，其实现了屏蔽和芯片之间的最小间隔。 没有通孔的第二屏蔽可以位于与第一屏蔽件相对的芯片的相对侧上。 在一组实施例中，硬化的铁流体屏蔽件可以是唯一的屏蔽件，或者该结构可以包括具有或不具有通孔的屏蔽件。 一组实施例包括具有通孔的外部屏蔽件，用于焊料访问固定到封装的外表面的封装接触焊盘。

公开(公告)号：US09029822B2

公开(公告)日：2015-05-12

申请号：US13843644

申请日：2013-03-15

Applicant: Avalanche Technology Inc.

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Dong Ha Jung

IPC: H01L27/112 ,  H01L27/24 ,  H01L27/115 ,  H01L27/22

CPC classification number: H01L27/11273 ,  H01L27/11556 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

Abstract: Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.

Abstract translation: 描述了以能够缩小到4F2的单位面积制造的电阻式存储单元阵列，其中F是技术节点中的最小特征尺寸。 一对电池中的存储单元通常包括在硅衬底中形成的沟槽底部的一对掩埋源。 源线与相邻单元共享。 一对栅电极在沟槽的侧壁上提供垂直沟道。 掩埋字线连接覆盖源极的侧壁上的栅极的底部，其中字线在阵列的末端环绕。 通过在对沟槽进行图案化之前，通过注入/掺杂硅的表面来形成与栅极自对准的漏极。 在漏极的顶部形成接触，并且在触点上制造电阻式存储元件。

公开(公告)号：US20140197505A1

公开(公告)日：2014-07-17

申请号：US13740180

申请日：2013-01-12

Applicant: AVALANCHE TECHNOLOGY INC.

Inventor： Yuchen Zhou ,  Bernardo Sardinha ,  Rajiv Yadav Ranjan ,  Ebrahim Abedifard ,  Roger Klas Malmhall ,  Zihui Wang ,  Yiming Huai ,  Jing Zhang

IPC: H01L43/02

CPC classification number: H01L23/552 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

Abstract: Chip packages are described with soft-magnetic shields that are included inside or attached externally to the package containing a MRAM chip. In one group of embodiments a single shield with vias for bonding wires is affixed to the surface of the MRAM chip having the contact pads. The limitation of shield to chip distance due to bonding wire is eliminated by VIA holes according to the invention which achieves minimal spacing between the shield and chip. A second shield without vias can be positioned on the opposite side of the chip from the first shield. In one group of embodiments a hardened ferro-fluid shield can be the only shield or the structure can include a shield with or without vias. One group of embodiments includes an external shield with vias for solder access to the package contact pads affixed to the outer surface of the package.

Abstract translation: 使用包含在包含MRAM芯片的封装内部或外部附加的软磁屏蔽来描述芯片封装。 在一组实施例中，具有用于接合线的通孔的单个屏蔽件固定到具有接触垫的MRAM芯片的表面上。 通过根据本发明的VIA孔消除了由于接合线导致的屏蔽到芯片距离的限制，其实现了屏蔽和芯片之间的最小间隔。 没有通孔的第二屏蔽可以位于与第一屏蔽件相对的芯片的相对侧上。 在一组实施例中，硬化的铁流体屏蔽件可以是唯一的屏蔽件，或者该结构可以包括具有或不具有通孔的屏蔽件。 一组实施例包括具有通孔的外部屏蔽件，用于焊料访问固定到封装的外表面的封装接触焊盘。

公开(公告)号：US20140170776A1

公开(公告)日：2014-06-19

申请号：US14096016

申请日：2013-12-04

Applicant: Avalanche Technology Inc.

Inventor： Kimihiro Satoh ,  Dong Ha Jung ,  Jing Zhang ,  Benjamin Chen ,  Yiming Huai ,  Rajiv Yadav Ranjan ,  Yuchen Zhou

IPC: H01L43/12

CPC classification number: H01L43/12

Abstract: Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.

Abstract translation: 描述了使用离子束蚀刻（IBE）对MRAM单元记忆元件的制造方法。 在本发明的实施例中，使用诸如RIE或磁化感应耦合等离子体（MICP）的反应蚀刻用一个掩模来蚀刻顶部电极和MTJ主体以提高选择性，然后使用如在各种替代实施例中所规定的IBE蚀刻底部电极 包括在IBE之前沉积的入射角，晶片旋转速率曲线和可选的钝化层的选择。 根据本发明的IBE通过使用由第一蚀刻阶段产生的层堆叠作为掩模来蚀刻底部电极而不需要附加掩模。 这使得底部电极与MTJ自对准。 国际教育局还实现了MTJ侧墙清洁，无需额外的步骤。

公开(公告)号：US20140138609A1

公开(公告)日：2014-05-22

申请号：US13843644

申请日：2013-03-15

Applicant: AVALANCHE TECHNOLOGY INC.

Inventor： Kimihiro Satoh ,  Yiming Huai ,  Jing Zhang ,  Dong Ha Jung

IPC: H01L27/24

CPC classification number: H01L27/11273 ,  H01L27/11556 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

Abstract: Resistive memory cell array fabricated with unit areas able to be scaled down to 4 F2, where F is minimum feature size in a technology node are described. Memory cells in a pair of cells commonly include a pair of buried sources in the bottom of trenches formed in a silicon substrate. The source line is shared with an adjacent cell. A pair of gate electrodes provides a vertical channel on a sidewall of the trench. A buried word line connects the bottom of the gates on the sidewall overlying the source wherein the word line is looped at the end of the array. A drain, which is self-aligned to the gate, is formed by implantation/doping the surface of the silicon before patterning the trenches. A contact is formed on top of the drain and the resistive memory element is fabrication on the contact.

Abstract translation: 描述了以能够缩小到4F2的单位面积制造的电阻式存储单元阵列，其中F是技术节点中的最小特征尺寸。 一对电池中的存储单元通常包括在硅衬底中形成的沟槽底部的一对掩埋源。 源线与相邻单元共享。 一对栅电极在沟槽的侧壁上提供垂直沟道。 掩埋字线连接覆盖源极的侧壁上的栅极的底部，其中字线在阵列的末端环绕。 通过在对沟槽进行图案化之前，通过注入/掺杂硅的表面来形成与栅极自对准的漏极。 在漏极的顶部形成接触，并且在触点上制造电阻式存储元件。