公开(公告)号：US09105343B2

公开(公告)日：2015-08-11

申请号：US14229647

申请日：2014-03-28

申请人： Avalanche Technology Inc.

发明人： Yuchen Zhou ,  Bing K Yen ,  Parviz Keshtbod ,  Mehdi Asnaashari

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C11/56

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1693 ,  G11C11/5607

摘要： The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of memory elements coupled in series. The method detects the resistance states of individual memory elements in an MLC by sequentially writing at least one of the plurality of memory element to the low resistance state in order of ascending write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

摘要翻译： 本发明涉及一种用于读取和写入STT-MRAM多电平单元（MLC）的方法，它包括串联耦合的多个存储单元。 该方法通过以上升写入电流阈值的顺序将多个存储元件中的至少一个依次写入低电阻状态来检测MLC中各个存储元件的电阻状态。 如果写入元件在写入步骤之后切换其电阻状态，则写入元件在写入步骤之前处于高电阻状态。 否则，写入元件在写入步骤之前处于低电阻状态。 根据本发明的实施例，可以通过比较在写入每个多个存储元件之前和之后的多个存储元件的电阻或电压值来确定电阻状态的切换。

公开(公告)号：US09070855B2

公开(公告)日：2015-06-30

申请号：US14053231

申请日：2013-10-14

申请人： Avalanche Technology Inc.

发明人： Huadong Gan ,  Yiming Huai ,  Yuchen Zhou ,  Xiaobin Wang ,  Zihui Wang ,  Bing K Yen

IPC分类号： H01L43/02 ,  H01F10/32 ,  G11C11/16 ,  H01F41/30 ,  H01L29/66 ,  H01L43/08 ,  H01L27/22 ,  H01L43/10 ,  B82Y40/00

CPC分类号： H01L27/228 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01L23/528 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

摘要翻译： 本发明涉及具有垂直磁隧道结（MTJ）存储元件的自旋转移转矩（STT）MRAM器件。 存储元件包括在非磁性种子层和非磁性覆盖层之间的垂直MTJ结构。 MTJ结构包括磁性自由层结构和介于其间的绝缘隧道结层的磁性参考层结构，与磁参考层结构相邻形成的反铁磁耦合层，以及邻近防反射层形成的磁性固定层， 铁磁耦合层。 无磁性和参考层结构中的至少一个包括非磁性垂直增强层，其改善与其相邻的磁性层的垂直各向异性。

公开(公告)号：US09123575B1

公开(公告)日：2015-09-01

申请号：US14336640

申请日：2014-07-21

申请人： Avalanche Technology, Inc.

发明人： Kimihiro Satoh ,  Bing K Yen ,  Dong Ha Jung ,  Yiming Huai

IPC分类号： H01L27/00 ,  H01L27/108 ,  H01L27/06 ,  H01L27/24 ,  H01L45/00 ,  H01L27/02 ,  H01L27/115

CPC分类号： H01L27/0207 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10855 ,  H01L27/11519 ,  H01L27/11565 ,  H01L27/228 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/085 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147

摘要： The present invention is directed to a semiconductor memory device including a plurality of first level contacts arranged in an array with every third row vacant along a first direction, thereby forming multiple contact regions separated by multiple vacant regions along the first direction with each of the multiple contact regions including a first row and a second row of the first level contacts extending along a second direction; a first and second plurality of second level contacts formed on top of the first level contacts with the second plurality of second level contacts having elongated shape extending into the vacant regions adjacent thereto; and a first and second plurality of memory elements formed on top of the first and second plurality of second level contacts, respectively, thereby permitting the memory elements to have greater center-to-center distance between two closest neighbors than the first level contacts.

摘要翻译： 本发明涉及一种半导体存储器件，其包括多个第一电平触点，每个第一电平触点沿阵列排列，每第三行沿着第一方向空置，从而形成多个接触区域，该接触区域沿多个空白区域沿第一方向分开， 包括沿第二方向延伸的第一级触点的第一行和第二行的接触区域; 形成在第一级顶部上的第一和第二多个第二级触点与第二多个第二级触点具有延伸到与其相邻的空缺区域中的细长形状; 以及分别形成在第一和第二多个第二电平触点的顶部上的第一和第二多个存储元件，从而允许存储元件在与第一电平触点之间的两个最接近的邻近之间具有更大的中心到中心距离。

公开(公告)号：US20140042571A1

公开(公告)日：2014-02-13

申请号：US14053231

申请日：2013-10-14

申请人： Avalanche Technology Inc.

发明人： Huadong Gan ,  Yiming Huai ,  Yuchen Zhou ,  Xiaobin Wang ,  Zihui Wang ,  Bing K Yen

IPC分类号： H01L43/02

CPC分类号： H01L27/228 ,  B82Y40/00 ,  G11C11/161 ,  H01F10/3286 ,  H01F10/329 ,  H01F41/302 ,  H01L23/528 ,  H01L27/222 ,  H01L29/66984 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention is directed to a spin transfer torque (STT) MRAM device having a perpendicular magnetic tunnel junction (MTJ) memory element. The memory element includes a perpendicular MTJ structure in between a non-magnetic seed layer and a non-magnetic cap layer. The MTJ structure comprises a magnetic free layer structure and a magnetic reference layer structure with an insulating tunnel junction layer interposed therebetween, an anti-ferromagnetic coupling layer formed adjacent to the magnetic reference layer structure, and a magnetic fixed layer formed adjacent to the anti-ferromagnetic coupling layer. At least one of the magnetic free and reference layer structures includes a non-magnetic perpendicular enhancement layer, which improves the perpendicular anisotropy of magnetic layers adjacent thereto.

摘要翻译： 本发明涉及具有垂直磁隧道结（MTJ）存储元件的自旋转移转矩（STT）MRAM器件。 存储元件包括在非磁性种子层和非磁性覆盖层之间的垂直MTJ结构。 MTJ结构包括磁性自由层结构和介于其间的绝缘隧道结层的磁性参考层结构，与磁参考层结构相邻形成的反铁磁耦合层，以及邻近防反射层形成的磁性固定层， 铁磁耦合层。 无磁性和参考层结构中的至少一个包括非磁性垂直增强层，其改善与其相邻的磁性层的垂直各向异性。

公开(公告)号：US08724380B1

公开(公告)日：2014-05-13

申请号：US14079518

申请日：2013-11-13

申请人： Avalanche Technology Inc.

发明人： Yuchen Zhou ,  Ebrahim Abedifard ,  Parviz Keshtbod ,  Mahmood Mozaffari ,  Kimihiro Satoh ,  Bing K Yen ,  Yiming Huai

IPC分类号： G11C13/00

CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/5607

摘要： The present invention is directed to a method for reading and writing an STT-MRAM multi-level cell (MLC), which includes a plurality of MTJ memory elements coupled in series. The method detects the resistance states of individual MTJ memory elements in an MLC by sequentially writing each memory element to the low resistance state in order of ascending parallelizing write current threshold. If a written element switches the resistance state thereof after the write step, then the written element was in the high resistance state prior to the write step. Otherwise, the written element was in the low resistance state prior to the write step. The switching of the resistance state can be ascertained by comparing the resistance or voltage values of the plurality of memory elements before and after writing each of the plurality of memory elements in accordance with the embodiments of the present invention.

摘要翻译： 本发明涉及一种用于读取和写入STT-MRAM多电平单元（MLC）的方法，其包括串联耦合的多个MTJ存储器元件。 该方法通过按照上升并行写入电流阈值的顺序将每个存储器元件顺序地写入低电阻状态来检测MLC中的各个MTJ存储器元件的电阻状态。 如果写入元件在写入步骤之后切换其电阻状态，则写入元件在写入步骤之前处于高电阻状态。 否则，写入元件在写入步骤之前处于低电阻状态。 根据本发明的实施例，可以通过比较在写入每个多个存储元件之前和之后的多个存储元件的电阻或电压值来确定电阻状态的切换。