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公开(公告)号：US20130173941A1
公开(公告)日：2013-07-04
申请号：US13780087
申请日：2013-02-28
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/206 , G06F1/324 , Y02D10/16
摘要： In one embodiment, the present invention includes a method for determining, in a controller of a multi-domain processor, whether a temperature of a second domain of the multi-domain processor is greater than a sum of a throttle threshold and a cross-domain margin, and if so, reducing a frequency of a first domain of the multi-domain processor by a selected amount. In this way, a temperature of the second domain can be allowed to reduce, given a thermal coupling of the domains. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于在多域处理器的控制器中确定多域处理器的第二域的温度是否大于节流阀阈值和跨域之和的方法 余量，如果是，则将多域处理器的第一域的频率降低所选择的量。 以这种方式，由于域的热耦合，可以允许第二域的温度降低。 描述和要求保护其他实施例。
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公开(公告)号：US20130080803A1
公开(公告)日：2013-03-28
申请号：US13247564
申请日：2011-09-28
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Itai Feit , Tomer Ziv , Doron Rajwan , Nadav Shulman , Alon Naveh
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Itai Feit , Tomer Ziv , Doron Rajwan , Nadav Shulman , Alon Naveh
CPC分类号： G01K7/42 , G06F1/206 , G06F1/3243 , Y02D10/152 , Y02D10/16 , Y02D50/20
摘要： In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定多核处理器的核心是否处于低功率状态的方法，如果是，则估计核心的温度并将估计的温度存储在第一核心的热存储区域中 。 通过使用该估计的温度，可以确定当其离开低功率状态时操作芯的适当电压。 描述和要求保护其他实施例。
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3.发明授权Estimating temperature of a processor core in a low power state without thermal sensor information 有权在没有热传感器信息的低功率状态下估计处理器内核的温度公开(公告)号：US09074947B2
公开(公告)日：2015-07-07
申请号：US13247564
申请日：2011-09-28
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Itai Feit , Tomer Ziv , Doron Rajwan , Nadav Shulman , Alon Naveh
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Itai Feit , Tomer Ziv , Doron Rajwan , Nadav Shulman , Alon Naveh
CPC分类号： G01K7/42 , G06F1/206 , G06F1/3243 , Y02D10/152 , Y02D10/16 , Y02D50/20
摘要： In one embodiment, the present invention includes a method for determining if a core of a multicore processor is in a low power state, and if so, estimating a temperature of the core and storing the estimated temperature in a thermal storage area for the first core. By use of this estimated temperature, an appropriate voltage at which to operate the core when it exits the low power state can be determined. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定多核处理器的核心是否处于低功率状态的方法，如果是，则估计核心的温度并将估计的温度存储在第一核心的热存储区域中 。 通过使用该估计的温度，可以确定当其离开低功率状态时操作芯的适当电压。 描述和要求保护其他实施例。
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4.发明申请公开(公告)号：US20140115351A1
公开(公告)日：2014-04-24
申请号：US14143939
申请日：2013-12-30
IPC分类号： G06F1/26
CPC分类号： G06F1/26 , G06F1/3243 , G06F9/5094 , Y02D10/152
摘要： In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于当前时间间隔确定多域处理器的功率预算的方法，确定要分配给处理器的第一和第二域的功率预算的一部分，以及控制频率 基于所分配的部分的域。 这样的确定和分配可以在处理器的运行期间动态地执行。 描述和要求保护其他实施例。
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公开(公告)号：US20130111120A1
公开(公告)日：2013-05-02
申请号：US13282896
申请日：2011-10-27
申请人： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells
发明人： Avinash N. Ananthakrishnan , Inder M. Sodhi , Efraim Rotem , Doron Rajwan , Eliezer Wiessman , Ryan Wells
CPC分类号： G06F1/324 , G06F1/3203 , G06F1/3293 , G06F1/3296 , G06F13/4068 , G06F13/4282 , G11C7/22 , Y02D10/122 , Y02D10/126 , Y02D10/151
摘要： In one embodiment, the present invention includes a processor having multiple domains including at least a core domain and a non-core domain that is transparent to an operating system (OS). The non-core domain can be controlled by a driver. In turn, the processor further includes a memory interconnect to interconnect the core domain and the non-core domain to a memory coupled to the processor. Still further, a power controller, which may be within the processor, can control a frequency of the memory interconnect based on memory boundedness of a workload being executed on the non-core domain. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括具有多个域的处理器，至少包括对于操作系统（OS）是透明的核心域和非核心域。 非核心域可以由驱动程序控制。 反过来，处理器还包括将核心域和非核心域互连到耦合到处理器的存储器的存储器互连。 此外，可以在处理器内的功率控制器可以基于在非核域上执行的工作负载的存储器有界性来控制存储器互连的频率。 描述和要求保护其他实施例。
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公开(公告)号：US09753516B2
公开(公告)日：2017-09-05
申请号：US13335628
申请日：2011-12-22
CPC分类号： G06F1/3206 , G06F1/324 , Y02D10/126
摘要： According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.
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公开(公告)号：US08539269B2
公开(公告)日：2013-09-17
申请号：US13077618
申请日：2011-03-31
申请人： Efraim Rotem , Avinash N. Ananthakrishnan , Doron Rajwan , Kosta Luria , Ronny Korner , Dan Baum
发明人： Efraim Rotem , Avinash N. Ananthakrishnan , Doron Rajwan , Kosta Luria , Ronny Korner , Dan Baum
IPC分类号： G06F1/32
CPC分类号： G06F1/30 , G06F1/28 , G06F1/3243 , G06F11/004 , G06F11/3024 , G06F11/3058 , G06F11/348 , G06F2201/81 , G06F2201/86 , Y02D10/152
摘要： An apparatus may comprise one or more processor cores of a processor and a set of current limiters. Each current limiter may be coupled to a respective processor core and arranged to monitor processor activity in the processor, to compare the processor activity to one or more current limits of multiple current limits; and to initiate a current-limiting action when the one or more current limits is exceeded.
摘要翻译： 设备可以包括处理器的一个或多个处理器核心和一组限流器。 每个限流器可以耦合到相应的处理器核心并且被布置成监视处理器中的处理器活动，以将处理器活动与多个电流限制的一个或多个电流限制进行比较; 并且当超过一个或多个电流限制时启动限流动作。
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公开(公告)号：US20130179705A1
公开(公告)日：2013-07-11
申请号：US13782539
申请日：2013-03-01
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessmann , Ryan Wells , Nadav Shulman
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Eliezer Wiessmann , Ryan Wells , Nadav Shulman
IPC分类号： G06F1/26
CPC分类号： G06F1/3206 , G06F1/26 , G06F1/324 , G06F1/3243 , G06F1/3287 , G06F9/3885 , Y02D10/126 , Y02D10/152 , Y02D10/171
摘要： In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.
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9.发明申请公开(公告)号：US20120221873A1
公开(公告)日：2012-08-30
申请号：US13335628
申请日：2011-12-22
IPC分类号： G06F1/32
CPC分类号： G06F1/3206 , G06F1/324 , Y02D10/126
摘要： According to one embodiment of the invention, an integrated circuit device comprises one or more processor cores and a control unit coupled to the processor core(s). The control unit is adapted to control an operating frequency of at least one processor core based on an estimated activity level in lieu of a power level. The estimated activity level differing from an estimated power level by being independent of leakage power and voltage characteristics particular to that integrated circuit device.
摘要翻译： 根据本发明的一个实施例，集成电路设备包括一个或多个处理器核和耦合到处理器核的控制单元。 控制单元适于基于代替功率电平的估计的活动水平来控制至少一个处理器核心的工作频率。 估计的活动水平与估计的功率水平不同，独立于该集成电路设备特有的泄漏功率和电压特性。
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10.发明授权Controlling operating frequency of a core domain via a non-core domain of a multi-domain processor 有权通过多域处理器的非核心域控制核心域的操作频率公开(公告)号：US09026815B2
公开(公告)日：2015-05-05
申请号：US13282947
申请日：2011-10-27
申请人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessmann , Ryan Wells
发明人： Avinash N. Ananthakrishnan , Efraim Rotem , Doron Rajwan , Jeremy J. Shrall , Eric C. Samson , Eliezer Wiessmann , Ryan Wells
CPC分类号： G06F1/324 , G06F1/26 , G06F1/30 , G06F1/3203 , G06F1/3234 , G06F1/3243 , G06F13/14 , Y02D10/126
摘要： In one embodiment, the present invention includes a method for determining that a non-core domain of a multi-domain processor is not operating at a frequency requested by the non-core domain, sending a request from the non-core domain to a power controller to reduce a frequency of a core domain of the multi-domain processor, and responsive to the request, reducing the core domain frequency. Other embodiments are described and claimed.
摘要翻译： 在一个实施例中，本发明包括一种用于确定多域处理器的非核心域不以非核域所请求的频率操作的方法，将来自非核心域的请求发送到功率 控制器降低多域处理器核心域的频率，并响应请求，降低核心域频率。 描述和要求保护其他实施例。
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