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41 条记录 (耗时 0.036 秒)

    Process for removing organic materials during formation of a metal interconnect
    3.
    发明授权
    Process for removing organic materials during formation of a metal interconnect 有权
    在形成金属互连件期间去除有机材料的方法

    公开(公告)号：US07122484B2

    公开(公告)日：2006-10-17

    申请号：US10833558

    申请日：2004-04-28

    申请人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

    发明人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

    IPC分类号： H01L21/469 ,  H01L21/44

    CPC分类号： H01L21/76814 ,  C11D3/3947 ,  C11D7/50 ,  C11D11/0047 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76808

    摘要： A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

    摘要翻译： 公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。 将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。 可以加入螯合剂以保护金属层免于氧化。 可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。 可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。 去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

    Measuring low dielectric constant film properties during processing
    6.
    发明授权
    Measuring low dielectric constant film properties during processing 有权
    在加工期间测量低介电常数膜性能

    公开(公告)号：US07400401B2

    公开(公告)日：2008-07-15

    申请号：US11096049

    申请日：2005-03-31

    申请人： Jang-Shiang Tsai ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Hun-Jan Tao

    发明人： Jang-Shiang Tsai ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Hun-Jan Tao

    IPC分类号： G01J4/00

    CPC分类号： G01N21/211

    摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.

    摘要翻译： 用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质 使用微波光谱仪恒定并导出介电常数的偶极分量。 测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

    Measuring low dielectric constant film properties during processing
    7.
    发明申请
    Measuring low dielectric constant film properties during processing 有权
    在加工期间测量低介电常数膜性能

    公开(公告)号：US20060220653A1

    公开(公告)日：2006-10-05

    申请号：US11096049

    申请日：2005-03-31

    申请人： Jang-Shiang Tsai ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Hun-Jan Tao

    发明人： Jang-Shiang Tsai ,  Peng-Fu Hsu ,  Baw-Ching Perng ,  Ju-Wang Hsu ,  Jyu-Horng Shieh ,  Yi-Nien Su ,  Hun-Jan Tao

    IPC分类号： G01R31/00 ,  G01N21/00 ,  G01J4/00

    CPC分类号： G01N21/211

    摘要： A method and system for determining the dielectric constant of a low-k dielectric film on a production substrate include measuring the electronic component of the dielectric constant using an ellipsometer, measuring the ionic component of the dielectric constant using an IR spectrometer, measuring the overall dielectric constant using a microwave spectrometer and deriving the dipolar component of the dielectric constant. The measurements and determination are non-contact and may be carried out on a production device that is further processed following the measurements.

    摘要翻译： 用于确定制造基板上的低k电介质膜的介电常数的方法和系统包括使用椭偏仪测量介电常数的电子部件，使用IR光谱仪测量介电常数的离子分量，测量总电介质 使用微波光谱仪恒定并导出介电常数的偶极分量。 测量和确定是非接触的，并且可以在进行测量后进一步处理的生产设备上进行。

    Process for patterning high-k dielectric material
    9.
    发明申请
    Process for patterning high-k dielectric material 有权
    图案化高k电介质材料的工艺

    公开(公告)号：US20050181590A1

    公开(公告)日：2005-08-18

    申请号：US11101774

    申请日：2005-04-08

    申请人： Hsien-Kuang Chiu ,  Baw-Ching Perng ,  Hun-Jan Tao

    发明人： Hsien-Kuang Chiu ,  Baw-Ching Perng ,  Hun-Jan Tao

    IPC分类号： C23F1/00 ,  H01L21/20 ,  H01L21/28 ,  H01L21/306 ,  H01L21/311 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L29/78

    CPC分类号： H01L21/31144 ,  H01L21/31116

    摘要： A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method further includes a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

    摘要翻译： 提供了一种图案化高k介电材料层的方法，其可用于制造半导体器件。 在高k电介质层上进行第一蚀刻。 在第一蚀刻之后，用第一蚀刻蚀刻的高k电介质层的一部分保留。 执行高k电介质层的第二蚀刻以去除高k电介质层的剩余部分。 第二蚀刻不同于第一蚀刻。 优选地，第一蚀刻是干蚀刻工艺，第二蚀刻是湿蚀刻工艺。 该方法还包括在第一次蚀刻之后和第二次蚀刻之前等离子体灰化高k电介质层的剩余部分的工艺。

    Integrated approach for controlling top dielectric loss during spacer etching
    10.
    发明授权
    Integrated approach for controlling top dielectric loss during spacer etching 有权
    在间隔蚀刻期间控制顶部介电损耗的集成方法

    公开(公告)号：US06498067B1

    公开(公告)日：2002-12-24

    申请号：US10139021

    申请日：2002-05-02

    申请人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

    发明人： Baw-Ching Perng ,  Ming-Huang Tsai ,  Ju-Wang Hsu ,  Hun-Jan Tao

    IPC分类号： H01L21336

    CPC分类号： H01L29/665 ,  H01L29/6656

    摘要： A process for forming a composite insulator spacer on the sides of a MOSFET gate structure, has been developed. The process features formation of additional insulator spacer shapes on top portions of sides of a gate structure in which an initial insulator spacer had been removed during an over etch cycle used for definition of the initial insulator spacer. The re-establishment of insulator spacer shapes provides a composite insulator spacer offering reduced risk of gate to substrate leakage or shorts, that can occur during a subsequent salicide procedure from the presence of metal silicide stringers or ribbons formed on, and residing on the composite insulator spacer.

    摘要翻译： 已经开发了在MOSFET栅极结构的侧面上形成复合绝缘体间隔物的工艺。 该工艺特征是在栅极结构的侧面的顶部部分上形成额外的绝缘体间隔物形状，其中在用于限定初始绝缘体间隔物的过蚀刻循环期间已经去除了初始绝缘体间隔物。 重新建立绝缘体间隔物形状提供了一种复合绝缘体间隔物，其降低了栅极与衬底泄漏或短路的风险，这可能在随后的自对准硅化物过程中发生，从存在金属硅化物桁条或形成在复合绝缘体上的带状物 间隔