公开(公告)号：US20050245082A1

公开(公告)日：2005-11-03

申请号：US10833558

申请日：2004-04-28

申请人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Sheu ,  Hun-Jan Tao

发明人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Sheu ,  Hun-Jan Tao

IPC分类号： C11D7/50 ,  C11D11/00 ,  G03F7/42 ,  H01L21/02 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768

CPC分类号： H01L21/76814 ,  C11D3/3947 ,  C11D7/50 ,  C11D11/0047 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76808

摘要： A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

摘要翻译： 公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。 将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。 可以加入螯合剂以保护金属层免于氧化。 可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。 可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。 去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

公开(公告)号：US07122484B2

公开(公告)日：2006-10-17

申请号：US10833558

申请日：2004-04-28

申请人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

发明人： Baw-Ching Perng ,  Yi-Chen Huang ,  Jun-Lung Huang ,  Bor-Wen Chan ,  Peng-Fu Hsu ,  Hsin-Ching Shih ,  Lawrance Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/469 ,  H01L21/44

CPC分类号： H01L21/76814 ,  C11D3/3947 ,  C11D7/50 ,  C11D11/0047 ,  G03F7/423 ,  H01L21/02063 ,  H01L21/02101 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/76808

摘要： A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.

摘要翻译： 公开了一种从基底上的低k电介质层和金属层上方的开口除去有机材料的方法。 将由一种或多种添加剂如羟胺或铵盐组成的臭氧水溶液作为喷雾或浸渍施用。 可以加入螯合剂以保护金属层免于氧化。 可以将二酮加入到臭氧水溶液中或在随后的步骤中以气相或液相的形式施加，以除去在臭氧处理期间形成的任何金属氧化物。 可以使用包括CO 2和臭氧的超临界流体混合物来除去不易被上述液体溶液剥离的有机残留物。 去除方法防止低k电介质层的介电常数和折射率的变化，并且清洁地去除提高器件性能的残留物。

公开(公告)号：US07354847B2

公开(公告)日：2008-04-08

申请号：US10764913

申请日：2004-01-26

申请人： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Tao

IPC分类号： H01L21/3205 ,  H01L27/10

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437

摘要： A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

摘要翻译： 描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。 在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。 通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。 通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

公开(公告)号：US06812044B2

公开(公告)日：2004-11-02

申请号：US10324465

申请日：2002-12-19

申请人： Hsien-Kuang Chiu ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Yuan-Hung Chiu ,  Hun-Jan Tao

发明人： Hsien-Kuang Chiu ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Yuan-Hung Chiu ,  Hun-Jan Tao

IPC分类号： H01L2100

CPC分类号： H01J37/32935 ,  H01L21/67069 ,  H01L21/67253

摘要： A method for monitoring plasma parameters during a plasma process such as a plasma etching process, comparing the measured plasma parameters to predetermined parameter specifications, and either terminating the plasma process or modifying the plasma process in progress to re-establish the plasma parameters within the parameter specifications. The plasma parameters may be measured by the self-excited electron resonance spectroscopy (SEEKS) technique or by microwave interferometry.

摘要翻译： 一种用于在诸如等离子体蚀刻工艺的等离子体工艺期间监测等离子体参数的方法，将测量的等离子体参数与预定参数规格进行比较，以及终止等离子体处理或修改正在进行的等离子体处理，以重新建立参数内的等离子体参数 规格。 等离子体参数可以通过自激电子共振光谱（SEEKS）技术或通过微波干涉测量来测量。

公开(公告)号：US20060009001A1

公开(公告)日：2006-01-12

申请号：US10864952

申请日：2004-06-10

申请人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

发明人： Yi-Chun Huang ,  Bor-Wen Chan ,  Baw-Ching Perng ,  Lawrence Sheu ,  Huan-Jan Tao ,  Chih-Hsin Ko ,  Chun-Chieh Lin

IPC分类号： H01L21/336 ,  H01L21/8234 ,  H01L21/76

CPC分类号： H01L29/66545 ,  H01L21/823807 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： Abstract of the Disclosure A method of forming a channel region for a MOSFET device in a strained silicon layer via employment of adjacent and surrounding silicon-germanium shapes, has been developed. The method features simultaneous formation of recesses in a top portion of a conductive gate structure and in portions of the semiconductor substrate not occupied by the gate structure or by dummy spacers located on the sides of the conductive gate structure. The selectively defined recesses will be used to subsequently accommodate silicon-germanium shapes, with the silicon-germanium shapes located in the recesses in the semiconductor substrate inducing the desired strained channel region. The recessing of the conductive gate structure and of semiconductor substrate portion reduces the risk of silicon-germanium bridging across the surface of sidewall spacers during epitaxial growth of the alloy layer, thus reducing the risk of gate to substrate leakage or shorts.

摘要翻译： 发明内容已经开发出通过使用相邻和周围的硅 - 锗形状在应变硅层中形成用于MOSFET器件的沟道区的方法。 该方法同时形成导电栅极结构的顶部中的凹部并且在半导体衬底的不被栅极结构占据的部分中，或者位于导电栅极结构的侧面上的虚设间隔物。 选择性限定的凹槽将用于随后容纳硅锗形状，其中硅 - 锗形状位于半导体衬底的凹陷中，从而诱导期望的应变通道区域。 导电栅极结构和半导体衬底部分的凹陷减少了在合金层的外延生长期间跨越侧壁间隔物表面的硅 - 锗桥接的风险，从而降低了栅极到衬底泄漏或短路的风险。

公开(公告)号：US07081413B2

公开(公告)日：2006-07-25

申请号：US10763688

申请日：2004-01-23

申请人： Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

发明人： Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/6656

摘要： A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

摘要翻译： 用于形成超窄半导体栅极结构的方法利用由氧化物衬垫覆盖的锥形硬掩模。 通过锥形蚀刻在半导体栅极材料上形成锥形硬掩模。 在半导体材料上形成锥形硬掩模结构之后，在锥形硬掩模上形成氧化物层。 执行高选择性蚀刻操作的序列以蚀刻半导体栅极材料的未覆盖部分，同时由锥形硬掩模和氧化物膜覆盖的栅极材料的部分保持未蚀刻以形成超窄栅极结构。

公开(公告)号：US20050164503A1

公开(公告)日：2005-07-28

申请号：US10763688

申请日：2004-01-23

申请人： Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

发明人： Bor-Wen Chan ,  Baw-Ching Perng ,  Ying-Tsung Chen

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/461

CPC分类号： H01L29/66545 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/6656

摘要： A method for forming an ultra narrow semiconductive gate structure utilizes a tapered hardmask covered by an oxide liner. The tapered hardmask is formed over the semiconductive gate material by tapered etching. After the tapered hardmask structure is formed over the semiconductive material, an oxide layer is formed over the tapered hardmask. A sequence of highly selective etch operations are carried out to etch uncovered portions of the semiconductive gate material while the portions of the gate material covered by the tapered hardmask and oxide film remain unetched to form ultra narrow gate structures.

摘要翻译： 用于形成超窄半导体栅极结构的方法利用由氧化物衬垫覆盖的锥形硬掩模。 通过锥形蚀刻在半导体栅极材料上形成锥形硬掩模。 在半导体材料上形成锥形硬掩模结构之后，在锥形硬掩模上形成氧化物层。 执行高选择性蚀刻操作的序列以蚀刻半导体栅极材料的未覆盖部分，同时由锥形硬掩模和氧化物膜覆盖的栅极材料的部分保持未蚀刻以形成超窄栅极结构。

公开(公告)号：US20050164478A1

公开(公告)日：2005-07-28

申请号：US10764913

申请日：2004-01-26

申请人： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Taq

发明人： Bor-Wen Chan ,  Yi-Chun Huang ,  Baw-Ching Perng ,  Hun-Jan Taq

IPC分类号： H01L21/027 ,  H01L21/033 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234

CPC分类号： H01L21/28123 ,  H01L21/0271 ,  H01L21/0338 ,  H01L21/31138 ,  H01L21/32137 ,  H01L21/32139 ,  H01L21/823437

摘要： A process for trimming a photoresist layer during the fabrication of a gate electrode in a MOSFET is described. A bilayer stack with a top photoresist layer on a thicker organic underlayer is patternwise exposed with 193 nm or 157 nm radiation to form a feature having a width w1 in the top layer. A pattern transfer through the underlayer is performed with an anisotropic etch based on H2/N2 and SO2 chemistry. The feature formed in the bilayer stack is trimmed by 10 nm or more to a width w2 by a HBr/O2/Cl2 plasma etch. The pattern transfer through an underlying gate layer is performed with a third etch based on HBr/O2/Cl2 chemistry. The underlayer is stripped by an O2 ashing with no damage to the gate electrode. Excellent profile control of the gate electrode is achieved and a larger (w1−w2) is possible than in prior art methods.

摘要翻译： 描述了在MOSFET的栅电极制造期间修整光致抗蚀剂层的工艺。 在较厚的有机底层上具有顶部光致抗蚀剂层的双层叠层以193nm或157nm辐射图案曝光以形成顶层中具有宽度w 1 1的特征。 通过底层的图案转移通过基于H 2 N 2 N 2 N 2 SO 3和SO 2 H 2化学的各向异性蚀刻进行。 通过HBr / O 2 / Cl 2等离子体将形成在双层叠层中的特征修剪10nm以上至宽度w 2 2 <！ - SIPO

公开(公告)号：US07241674B2

公开(公告)日：2007-07-10

申请号：US10846278

申请日：2004-05-13

申请人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Jyu-Horng Shieh ,  Hun-Jan Tao

IPC分类号： H01L21/3205 ,  H01L21/336

CPC分类号： H01L29/66507 ,  H01L21/28097

摘要： A method of forming a silicided gate on a substrate having active regions is provided. The method comprises forming silicide in the active regions and a portion of the gate, leaving a remaining portion of the gate unsilicided; forming a shielding layer over the active regions and gate after the forming step; forming a coating layer over portions of the shielding layer over the active regions; opening the shielding layer to expose the gate, wherein the coating layer protects the portions of the shielding layer over the active regions during the opening step; depositing a metal layer over the exposed gate; and annealing to cause the metal to react with the gate to silicidize at least a part of the remaining portion of the gate.

摘要翻译： 提供了在具有活性区域的基板上形成硅化栅的方法。 该方法包括在有源区和栅极的一部分上形成硅化物，留下栅极的剩余部分未被硅化; 在成形步骤之后在有源区和栅上形成屏蔽层; 在所述有源区上的所述屏蔽层的部分上形成涂层; 打开所述屏蔽层以暴露所述栅极，其中所述涂层在所述打开步骤期间保护所述屏蔽层的所述部分在所述有源区域上方; 在暴露的栅极上沉积金属层; 并退火以使金属与栅极反应，使栅极的剩余部分的至少一部分硅化。

公开(公告)号：US20050179098A1

公开(公告)日：2005-08-18

申请号：US10780513

申请日：2004-02-17

申请人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

发明人： Bor-Wen Chan ,  Chih-Hao Wang ,  Lawrance Hsu ,  Hun-Jan Tao

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L29/6659 ,  H01L21/28097 ,  H01L21/823425 ,  H01L21/823443 ,  H01L21/823462 ,  H01L21/823835 ,  H01L21/823857 ,  H01L29/4975 ,  H01L29/66545 ,  H01L29/7833

摘要： A new method to form metal silicide gates in the fabrication of an integrated circuit device is achieved. The method comprises forming polysilicon lines overlying a substrate with a dielectric layer therebetween. A first isolation layer is formed overlying the substrate and the sidewalls of the polysilicon lines. The first isolation layer does not overlie the top surface of the polysilicon lines. The polysilicon lines are partially etched down such that the top surfaces of the polysilicon lines are below the top surface of the first isolation layer. A metal layer is deposited overlying the polysilicon lines. A thermal anneal is used to completely convert the polysilicon lines to metal silicide gates. The unreacted metal layer is removed to complete the device.

摘要翻译： 实现了在制造集成电路器件中形成金属硅化物栅极的新方法。 该方法包括在其间具有介电层的衬底上形成多晶硅线。 第一隔离层形成在衬底和多晶硅线的侧壁上。 第一隔离层不覆盖多晶硅线的顶表面。 多晶硅线被部分地向下蚀刻，使得多晶硅线的顶表面在第一隔离层的顶表面下方。 金属层沉积在多晶硅线上。 使用热退火将多晶硅线完全转换成金属硅化物栅极。 去除未反应的金属层以完成该装置。