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1.发明申请Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US20080237573A1
公开(公告)日：2008-10-02
申请号：US11731266
申请日：2007-03-29
IPC分类号： H01L29/06
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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2.发明申请Mechanism for Forming a Remote Delta Doping Layer of a Quantum Well Structure 有权形成量子阱结构的远程三角形掺杂层的机理公开(公告)号：US20100219396A1
公开(公告)日：2010-09-02
申请号：US12715034
申请日：2010-03-01
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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3.发明授权Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US08264004B2
公开(公告)日：2012-09-11
申请号：US12715034
申请日：2010-03-01
IPC分类号： H01L29/778
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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4.发明授权Mechanism for forming a remote delta doping layer of a quantum well structure 有权用于形成量子阱结构的远程δ掺杂层的机理公开(公告)号：US07713803B2
公开(公告)日：2010-05-11
申请号：US11731266
申请日：2007-03-29
IPC分类号： H01L21/336
CPC分类号： H01L29/161 , H01L29/1054 , H01L29/517 , H01L29/7782 , H01L29/78
摘要： A method of fabricating a quantum well device includes forming a diffusion barrier on sides of a delta layer of a quantum well to confine dopants to the quantum well.
摘要翻译： 制造量子阱器件的方法包括在量子阱的δ层的侧面上形成扩散阻挡层，以将掺杂剂限制在量子阱中。
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公开(公告)号：US20070145468A1
公开(公告)日：2007-06-28
申请号：US11322089
申请日：2005-12-28
申请人： Amlan Majumdar , Suman Datta , Been-Yih Jin , Mark Doczy , Robert Chau
发明人： Amlan Majumdar , Suman Datta , Been-Yih Jin , Mark Doczy , Robert Chau
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , B82Y10/00 , H01L27/115 , H01L29/40114 , H01L29/42332 , H01L29/66825
摘要： Some embodiments of the present invention include apparatuses and methods relating to nonvolatile memory transistors.
摘要翻译： 本发明的一些实施例包括与非易失性存储晶体管相关的装置和方法。
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6.发明申请Narrow-body multiple-gate FET with dominant body transistor for high performance 审中-公开具有主体晶体管的窄体多栅极FET，用于高性能公开(公告)号：US20070090408A1
公开(公告)日：2007-04-26
申请号：US11240487
申请日：2005-09-29
申请人： Amlan Majumdar , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Matthew Metz , Marko Radosavljevic , Been-Yih Jin , Robert Chau
发明人： Amlan Majumdar , Suman Datta , Brian Doyle , Jack Kavalieros , Justin Brask , Matthew Metz , Marko Radosavljevic , Been-Yih Jin , Robert Chau
IPC分类号： H01L29/76
CPC分类号： H01L29/66795 , H01L29/66545 , H01L29/785 , H01L29/7854
摘要： A field-effect transistor for a narrow-body, multiple-gate transistor such as a FinFET, tri-gate or Ω-FET is described. The corners of the channel region disposed beneath the gate are rounded n, for instance, oxidation steps, to reduce the comer effect associated with conduction initiating in the corners of the channel region.
摘要翻译： 描述了用于诸如FinFET，三栅极或者Omega-FET的窄体多栅极晶体管的场效应晶体管。 设置在栅极下方的通道区域的角部是圆形的，例如氧化步骤，以减少与沟道区域的拐角中的传导起始相关的拐角效应。
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公开(公告)号：US07858481B2
公开(公告)日：2010-12-28
申请号：US11154138
申请日：2005-06-15
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
摘要翻译： 描述了制造具有减薄沟道区的MOS晶体管的方法。 在去除虚拟栅极之后蚀刻沟道区。 源极和漏极区域具有相对较低的电阻。
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公开(公告)号：US20090283496A1
公开(公告)日：2009-11-19
申请号：US11391920
申请日：2006-03-28
CPC分类号： B82Y40/00 , B82Y30/00 , C01B32/162
摘要： Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.
摘要翻译： 本发明的实施例包括与使用图案化层的定向碳纳米管生长相关的装置和方法。 在一些实施方案中，图案化层包括引导碳纳米管生长的抑制剂材料。
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9.发明申请FABRICATION OF CHANNEL WRAPAROUND GATE STRUCTURE FOR FIELD-EFFECT TRANSISTOR 审中-公开用于场效应晶体管的通道封口结构的制造公开(公告)号：US20160308014A1
公开(公告)日：2016-10-20
申请号：US15197563
申请日：2016-06-29
申请人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Justin K. Brask , Robert S. Chau
发明人： Marko Radosavljevic , Amlan Majumdar , Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Justin K. Brask , Robert S. Chau
IPC分类号： H01L29/423 , H01L29/66 , H01L29/06 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/28079 , H01L21/28194 , H01L29/0673 , H01L29/41775 , H01L29/495 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/66545 , H01L29/6656 , H01L29/66606 , H01L29/66636 , H01L29/66742 , H01L29/7834 , H01L29/78618 , H01L29/78696 , Y10S438/926 , Y10S438/957
摘要： A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.
摘要翻译： 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。
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公开(公告)号：US09337307B2
公开(公告)日：2016-05-10
申请号：US12949696
申请日：2010-11-18
申请人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
发明人： Justin K. Brask , Robert S. Chau , Suman Datta , Mark L. Doczy , Brian S. Doyle , Jack T. Kavalieros , Amlan Majumdar , Matthew V. Metz , Marko Radosavljevic
IPC分类号： H01L29/66 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7848 , H01L29/0649 , H01L29/0847 , H01L29/1033 , H01L29/161 , H01L29/165 , H01L29/24 , H01L29/267 , H01L29/4236 , H01L29/42376 , H01L29/4966 , H01L29/66545 , H01L29/66621 , H01L29/66628 , H01L29/66636 , H01L29/66818 , H01L29/7834 , H01L29/7838 , H01L29/785 , H04B1/3827 , Y10S438/926
摘要： A method of fabricating a MOS transistor having a thinned channel region is described. The channel region is etched following removal of a dummy gate. The source and drain regions have relatively low resistance with the process.
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